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| SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1700 Series USER'S MANUAL General Release Specification SN8P1702 SN8P1704 SN8P1706 SN8P1707 SN8P1708 SONiX 8-Bit Micro-Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. SONiX TECHNOLOGY CO., LTD Page 1 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC AMENDMENT HISTORY Version VER 1.90 VER 1.93 Date Sep. 2002 Feb. 2003 Description V1.90 first issue 1. Extend chip operating temperature from "0C ~ +70C" to "-20C ~ +70C". 2. Change the description of ADD M,A instruction from "M 3. Add ADC grade table. 4. Remove "Support hardware multiplier (MUL)" in SN8P1702 FEATURES section. 5. Change "Four internal interrupts" to "Three internal interrupts" in SN8P1704 FEATURES section. 6. Change "ACC can't be access by "B0MOV" instruction" to "ACC can't be access by "B0MOV" instruction during the instant addressing mode". 7. Correct the description of STKnH. 8. Change "special register is located at 08h~FFh" to "special register is located at 80h~FFh". 9. Correct the bit definition of INTEN register. 10. Correct the description of "TC0 CLOCK FREQUENCY OUTPUT" section. 11. Correct the description of "TC1 CLOCK FREQUENCY OUTPUT" section. 12. SCKMD = 1 means SIO is in SLAVE mode. SCKMD = 0 means SIO is in MASTER mode. 13. Remove "SIO clock and SPI clock are compatible". 14. Modify ADB's output data table. 15. Correct an error of template code: "b0bclr FWDRST" 16. Add a notice about OSCM register access cycle. 17. SN8P1702/SN8A1702A don't provide "MUL, PUSH, POP" instruction. 18. Add a notice about OSCM register access cycle. VER 1.94 Sep. 2003 1. Correct EOC description. 2. Correct watchdog timer overflow time. 3. Correct POP operand. 4. Correct ADCKS table. 5. Add new section about checksum calculate must avoid 04H~07H. 6. Reserved Last 16 word ROM addresses 7. Add SIOM table and SIO rate note 8. Remove register bit description 9. Modify TC0M description 10. Modify TC1M description 11. Modify PWM description 12. Modify ADC Frequency description 13. Change Code option table to Chapter 2 14. Add ADC current consumption "b0bset FWDRST". M+A" to "M A+M" SONiX TECHNOLOGY CO., LTD Page 2 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 15. Add LVD detect voltage 16. Remove approval sheet. 17. Remove PCB layout notice section. 18. Add MASK/OTP relative table. 19. Modify the description of INTRQ register. 20. Modify the calculation formula of SIOR and SIO clock. SONiX TECHNOLOGY CO., LTD Page 3 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Table of Contents AMENDMENT HISTORY .............................................................................................................. 2 1 PRODUCT OVERVIEW ................................................................................................... 11 GENERAL DESCRIPTION ......................................................................................................... 11 FEATURES SELECTION TABLE....................................................................................... 11 MASK/OTP RELATIVE TABLE ................................................................................................. 11 ADC GRADE TABLE............................................................................................................. 11 SN8P1702 FEATURES............................................................................................................... 12 SN8P1704 FEATURES............................................................................................................... 13 SN8P1707/SN8P1708 FEATURES ............................................................................................ 15 SYSTEM BLOCK DIAGRAM ...................................................................................................... 16 PIN ASSIGNMENT ..................................................................................................................... 17 PIN DESCRIPTIONS .................................................................................................................. 22 PIN CIRCUIT DIAGRAMS .......................................................................................................... 22 2 3 CODE OPTION TABLE ................................................................................................... 23 ADDRESS SPACES ........................................................................................................ 24 PROGRAM MEMORY (ROM)..................................................................................................... 24 OVERVIEW ............................................................................................................................. 24 USER RESET VECTOR ADDRESS (0000H).......................................................................... 26 INTERRUPT VECTOR ADDRESS (0008H) ............................................................................ 26 CHECKSUM CALCULATION .................................................................................................. 28 GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................. 29 LOOKUP TABLE DESCRIPTION............................................................................................ 29 JUMP TABLE DESCRIPTION................................................................................................. 31 DATA MEMORY (RAM) .............................................................................................................. 33 OVERVIEW ............................................................................................................................. 33 SONiX TECHNOLOGY CO., LTD Page 4 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC RAM BANK SELECTION ........................................................................................................ 35 WORKING REGISTERS............................................................................................................. 36 H, L REGISTERS .................................................................................................................... 36 Y, Z REGISTERS .................................................................................................................... 37 X REGISTERS ........................................................................................................................ 38 R REGISTERS ........................................................................................................................ 38 PROGRAM FLAG ....................................................................................................................... 39 CARRY FLAG ......................................................................................................................... 39 DECIMAL CARRY FLAG......................................................................................................... 39 ZERO FLAG ............................................................................................................................ 39 ACCUMULATOR ........................................................................................................................ 40 STACK OPERATIONS................................................................................................................ 41 OVERVIEW ............................................................................................................................. 41 STACK REGISTERS............................................................................................................... 42 STACK OPERATION EXAMPLE............................................................................................. 43 PROGRAM COUNTER............................................................................................................... 44 ONE ADDRESS SKIPPING .................................................................................................... 45 MULTI-ADDRESS JUMPING .................................................................................................. 46 4 5 ADDRESSING MODE...................................................................................................... 47 OVERVIEW................................................................................................................................. 47 IMMEDIATE ADDRESSING MODE ........................................................................................ 47 DIRECTLY ADDRESSING MODE .......................................................................................... 47 INDIRECTLY ADDRESSING MODE....................................................................................... 47 TO ACCESS DATA in RAM BANK 0....................................................................................... 48 TO ACCESS DATA in RAM BANK 1....................................................................................... 48 SYSTEM REGISTER ....................................................................................................... 49 OVERVIEW................................................................................................................................. 49 SYSTEM REGISTER ARRANGEMENT (BANK 0) ..................................................................... 49 BYTES of SYSTEM REGISTER.............................................................................................. 49 BITS of SYSTEM REGISTER ................................................................................................. 51 SONiX TECHNOLOGY CO., LTD Page 5 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 6 7 POWER ON RESET ........................................................................................................ 55 OVERVIEW................................................................................................................................. 55 EXTERNAL RESET DESCRIPTION........................................................................................... 56 LOW VOLTAGE DETECTOR (LVD) DESCRIPTION.................................................................. 57 OSCILLATORS................................................................................................................ 58 OVERVIEW................................................................................................................................. 58 CLOCK BLOCK DIAGRAM ..................................................................................................... 58 OSCM REGISTER DESCRIPTION ......................................................................................... 59 EXTERNAL HIGH-SPEED OSCILLATOR............................................................................... 60 OSCILLATOR MODE CODE OPTION .................................................................................... 60 OSCILLATOR DEVIDE BY 2 CODE OPTION......................................................................... 60 OSCILLATOR SAFE GUARD CODE OPTION ....................................................................... 60 SYSTEM OSCILLATOR CIRCUITS ........................................................................................ 61 External RC Oscillator Frequency Measurement .................................................................... 62 INTERNAL LOW-SPEED OSCILLATOR .................................................................................... 63 SYSTEM MODE DESCRIPTION ................................................................................................ 64 OVERVIEW ............................................................................................................................. 64 NORMAL MODE ..................................................................................................................... 64 SLOW MODE .......................................................................................................................... 64 POWER DOWN MODE........................................................................................................... 64 SYSTEM MODE CONTROL ....................................................................................................... 65 SN8P1700 SYSTEM MODE BLOCK DIAGRAM ..................................................................... 65 SYSTEM MODE SWITCHING ................................................................................................ 66 WAKEUP TIME........................................................................................................................... 67 OVERVIEW ............................................................................................................................. 67 HARDWARE WAKEUP ........................................................................................................... 67 8 TIMERS COUNTERS....................................................................................................... 68 WATCHDOG TIMER (WDT) ....................................................................................................... 68 BASIC TIMER 0 (T0) .................................................................................................................. 69 SONiX TECHNOLOGY CO., LTD Page 6 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC OVERVIEW ............................................................................................................................. 69 T0M REGISTER DESCRIPTION ............................................................................................ 69 T0C COUNTING REGISTER .................................................................................................. 70 T0 BASIC TIMER OPERATION SEQUENCE ......................................................................... 71 TIMER COUNTER 0 (TC0) ......................................................................................................... 72 OVERVIEW ............................................................................................................................. 72 TC0M MODE REGISTER........................................................................................................ 73 TC0C COUNTING REGISTER................................................................................................ 74 TC0R AUTO-LOAD REGISTER .............................................................................................. 75 TC0 TIMER COUNTER OPERATION SEQUENCE................................................................ 76 TC0 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................... 78 TC0OUT FREQUENCY TABLE .................................................................................................. 79 TIMER COUNTER 1 (TC1) ......................................................................................................... 81 OVERVIEW ............................................................................................................................. 81 TC1M MODE REGISTER........................................................................................................ 82 TC1C COUNTING REGISTER................................................................................................ 83 TC1R AUTO-LOAD REGISTER .............................................................................................. 84 TC1 TIMER COUNTER OPERATION SEQUENCE................................................................ 85 TC1 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................... 87 PWM FUNCTION DESCRIPTION .............................................................................................. 88 OVERVIEW ............................................................................................................................. 88 PWM PROGRAM DESCRIPTION........................................................................................... 89 9 INTERRUPT..................................................................................................................... 90 OVERVIEW................................................................................................................................. 90 INTEN INTERRUPT ENABLE REGISTER ................................................................................. 91 INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 91 INTERRUPT OPERATION DESCRIPTION ................................................................................ 92 GIE GLOBAL INTERRUPT OPERATION ............................................................................... 92 INT0 (P0.0) INTERRUPT OPERATION .................................................................................. 93 INT1 (P0.1) INTERRUPT OPERATION .................................................................................. 93 INT2 (P0.2) INTERRUPT OPERATION .................................................................................. 94 T0 INTERRUPT OPERATION................................................................................................. 95 TC0 INTERRUPT OPERATION .............................................................................................. 96 TC1 INTERRUPT OPERATION .............................................................................................. 97 SIO INTERRUPT OPERATION............................................................................................... 98 MULTI-INTERRUPT OPERATION .......................................................................................... 99 SONiX TECHNOLOGY CO., LTD Page 7 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 10 SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) ................................................ 101 OVERVIEW............................................................................................................................... 101 SIOM MODE REGISTER.......................................................................................................... 102 SIOB DATA BUFFER................................................................................................................ 103 SIOR REGISTER DESCRIPTION ............................................................................................ 103 SIO MASTER OPERATING DESCRIPTION ............................................................................ 104 RISING EDGE TRANSMITTER/RECEIVER MODE.............................................................. 104 FALLING EDGE TRANSMITTER/RECEIVER MODE ........................................................... 105 RISING EDGE RECEIVER MODE ........................................................................................ 106 FALLING EDGE RECEIVER MODE ..................................................................................... 107 SIO SLAVE OPERATING DESCRIPTION................................................................................ 108 RISING EDGE TRANSMITTER/RECEIVER MODE.............................................................. 109 FALLING EDGE TRANSMITTER/RECEIVER MODE ........................................................... 110 RISING EDGE RECEIVER MODE ........................................................................................ 111 FALLING EDGE RECEIVER MODE ..................................................................................... 112 SIO INTERRUPT OPERATION DESCRIPTION....................................................................... 113 11 12 I/O PORT............................................................................................................. 114 OVERVIEW............................................................................................................................... 114 I/O PORT FUNCTION TABLE .................................................................................................. 115 PULL-UP RESISTERS.............................................................................................................. 116 I/O PORT DATA REGISTER .................................................................................................... 119 8-CHANNEL ANALOG TO DIGITAL CONVERTER........................................... 121 OVERVIEW............................................................................................................................... 121 ADM REGISTER....................................................................................................................... 122 ADR REGISTERS..................................................................................................................... 122 ADB REGISTERS ..................................................................................................................... 122 ADC CONVERTING TIME ........................................................................................................ 124 ADC CIRCUIT........................................................................................................................... 125 SONiX TECHNOLOGY CO., LTD Page 8 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 13 14 15 16 17 7-BIT DIGITAL TO ANALOG CONVERTER ...................................................... 126 OVERVIEW............................................................................................................................... 126 DAM REGISTER....................................................................................................................... 126 D/A CONVERTER OPERATION .............................................................................................. 127 CODING ISSUE .................................................................................................. 128 TEMPLATE CODE.................................................................................................................... 128 CHIP DECLARATION IN ASSEMBLER.................................................................................... 133 PROGRAM CHECK LIST ......................................................................................................... 133 INSTRUCTION SET TABLE ............................................................................... 134 ELECTRICAL CHARACTERISTIC ..................................................................... 135 ABSOLUTE MAXIMUM RATING .............................................................................................. 135 STANDARD ELECTRICAL CHARACTERISTIC ....................................................................... 135 SN8P1700 Series (OTP) ....................................................................................................... 135 PACKAGE INFORMATION ................................................................................ 136 P-DIP18 PIN ............................................................................................................................. 136 SOP18 PIN ............................................................................................................................... 137 SSOP20 PIN ............................................................................................................................. 138 S-DIP28 PIN ............................................................................................................................. 139 SOP28 PIN ............................................................................................................................... 140 QFP 44 PIN............................................................................................................................... 141 SSOP 48 PIN ............................................................................................................................ 142 SONiX TECHNOLOGY CO., LTD Page 9 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC P-DIP 48 PIN ............................................................................................................................ 143 P-DIP 40 PIN ............................................................................................................................ 144 SONiX TECHNOLOGY CO., LTD Page 10 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 1 PRODUCT OVERVIEW GENERAL DESCRIPTION The SN8P1700 is a series of 8-bit micro-controller including SN8P1702, SN8P1704, SN8P1706, SN8P1707 and SN8P1708. This series is utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure. These chips are designed with the excellent IC structure including the large program memory OTP ROM, the massive data memory RAM, one 8-bit basic timer (T0), two 8-bit timer counters (TC0, TC1), a watchdog timer, up to seven interrupt sources (T0, TC0, TC1, SIO, INT0, INT1, INT2), a 7-bit DAC converter, an 8-channel ADC converter with 8-bit/12-bit resolution, two channel PWM output (PWM0, PWM1), tw0 channel buzzer output (BZ0, BZ1) and 8-level stack buffers. Besides, the user can choose desired oscillator configurations for the controller. There are four oscillator configurations to select for generating system clock, including High/Low Speed crystal, ceramic resonator or cost-saving RC. SN8P1700 series also includes an internal RC oscillator for slow mode controlled by programming. FEATURES SELECTION TABLE CHIP SN8P1702 SN8P1704 SN8P1706 SN8P1707 SN8P1708 4K*16 256 ROM RAM Stack 1K*16 2K*16 64 128 8 V V V Timer T0 TC0 TC1 V V V V V V V V V 12 18 30 33 33 4ch 5ch 8ch 8ch 8ch 1ch 1ch 1ch 1ch I/O ADC DAC PWM Buzzer 1 2 2 2 2 1 1 1 1 SIO Wakeup Pin no. 3 8 9 9 9 DIP18/SOP18 Package SKDIP28/SOP28 DIP40 QFP44 DIP48/SSOP48 Table 1-1. Selection Table of SN8P1700 MASK/OTP Relative Table Mask Version SN8A1702A SN8A1704A SN8A1706A SN8A1707A SN8A1708A Package Form DIP18/SOP18/SSOP20 SKDIP28/SOP28 DIP40 QFP44 DIP48/SSOP48 OTP Chip for Verification SN8P1702 SN8P1704 SN8P1706 SN8P1707 SN8P1708 Assembler Declaration CHIP SN8P1702 CHIP SN8P1704 CHIP SN8P1706 CHIP SN8P1707 CHIP SN8P1708 Note: Recommend SN8P1702A to replace SN8P1702 in new design. Refer SN8P1702A datasheet for details. Table 1-2. MASK/OTP Relative Table ADC GRADE TABLE CHIP SN8P170X PARAMETER Resolution No Mission Code Differential Nonlinearity (DNL) Resolution No Mission Code Differential Nonlinearity (DNL) MIN 8 MAX 12 12 16 12 12 4 UNITS Bits Bits LSB Bits Bits LSB REMARK 170X: 1702~1708 170X: 1702~1708 SN8P170X-12 10 Table 1-3. ADC Grade Table SONiX TECHNOLOGY CO., LTD Page 11 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1702 FEATURES Memory configuration OTP ROM size: 1K * 16 bits. RAM size: 64 * 8 bits. I/O pin configuration (Total 12 pins) Input only: P0 Bi-directional: P1, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. One 8-bit timer counters. (TC0). On chip watchdog timer. Eight levels stack buffer. 59 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Two interrupt sources One internal interrupts: TC0. One external interrupts: INT0. An 4-channel ADC with 8-bit/12-bit resolution One channel PWM output. (PWM0) One channel Buzzer output. (BZ0) Dual clock system offers three operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Package (Chip form support) PDIP 18 pins SOP 18 pins / SSOP20 (MASK type only) Notice: 1. Declare "CHIP SN8P1702" in assembler. 2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information 3. Call @SET_PUR macro at least one time to avoid sleep mode fail. SONiX TECHNOLOGY CO., LTD Page 12 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1704 FEATURES Memory configuration OTP ROM size: 2K * 16 bits. RAM size: 128 * 8 bits. I/O pin configuration (Total 18 pins) Input only: P0 Bi-directional: P1, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. Two 8-bit timer counters. (TC0, TC1). On chip watchdog timer. Eight levels stack buffer. 60 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). Six interrupt sources Three internal interrupts: TC0, TC1, SIO. Three external interrupts: INT0, INT1, INT2. A 5-channel ADC with 8-bit/12-bit resolution. One channel DAC with 7-bit resolution. SIO function. Two channel PWM output. (PWM0, PWM1) Two channel Buzzer output. (BZ0, BZ1) Dual clock system offers three operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Package (Chip form support) SOP 28 pins SKDIP 28 pins Notice: 1. Declare "CHIP SN8P1704" in assembler. 2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information 3. Call @SET_PUR macro at least one time to avoid sleep mode fail. SONiX TECHNOLOGY CO., LTD Page 13 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1706 FEATURES Memory configuration OTP ROM size: 4K * 16 bits. RAM size: 256 * 8 bits (bank 0 and bank 1). I/O pin configuration (Total 30 pins) Input only: P0 Bi-directional: P1, P2, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P2, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. An 8-bit basic timer. (T0). Two 8-bit timer counters. (TC0, TC1). On chip watchdog timer. Eight levels stack buffer. 60 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). Seven interrupt sources Four internal interrupts: T0, TC0, TC1, SIO. Three external interrupts: INT0, INT1, INT2. An 8-channel ADC with 8-bit/12-bit resolution. One channel DAC 7bit resolution. SIO function. Two channel PWM output. (PWM0, PWM1) Two channel Buzzer output. (BZ0, BZ1) Dual clock system offers three operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Package (Chip form support) P-DIP 40 pins Notice: 1. Declare "CHIP SN8P1706" in assembler. 2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information SONiX TECHNOLOGY CO., LTD Page 14 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1707/SN8P1708 FEATURES Memory configuration OTP ROM size: 4K * 16 bits. RAM size: 256 * 8 bits (bank 0 and bank 1). I/O pin configuration (Total 33 pins) Input only: P0 Bi-directional: P1, P2, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P2, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. An 8-bit basic timer. (T0). Two 8-bit timer counters. (TC0, TC1). On chip watchdog timer. Eight levels stack buffer. 60 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). Seven interrupt sources Four internal interrupts: T0, TC0, TC1, SIO. Three external interrupts: INT0, INT1, INT2. An 8-channel ADC with 8-bit/12-bit resolution. One channel DAC with 7-bit resolution. SIO function. Two channel PWM output. (PWM0, PWM1) Two channel Buzzer output. (BZ0, BZ1) Dual clock system offers three operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only Sleep mode: Both high and low clock stop Package (Chip form support) QPF 44 pins (SN8P1707) SSOP 48 pins (SN8P1708) PDIP 48 pins (SN8P1708) Notice: 1. Declare "CHIP SN8P1707" for SN8P1707 in assembler. 2. Declare "CHIP SN8P1708" for SN8P1708 in assembler. 3. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information SONiX TECHNOLOGY CO., LTD Page 15 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SYSTEM BLOCK DIAGRAM PC IR FLAGS OTP ROM TIMING GENERATOR PWM0 PWM1/Buzzer1 PWM1 H-OSC Internal CLK Low Volt Detector Watch-Dog Timer PWM0/Buzzer0 ALU RAM DAC DAO AIN0~AIN7 ACC SYSTEM REGISTER ADC INTERRUPT CONTROL PORT 0 SIO TX/RX TIMER & COUNTER PORT 1 PORT 2 PORT 4 PORT 5 Figure 1-1.Simplified System Block Diagram SONiX TECHNOLOGY CO., LTD Page 16 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PIN ASSIGNMENT Format DescriptionSN8P17XXY Y = Q > QFPP > PDIPK > SKDIPS > SOPX> SSOP OTP Type: SN8P1702 (SOP 18PIN) SN8P1702 (PDIP 18PIN) P0.0/INT0 RST P1.1 P1.0 VSS P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SN8P1702P SN8P1702S VDD/VPP XIN XOUT P5.0 P5.1 P5.2 P5.3 P5.4/BZ0/PWM0 VDD MASK Type: SN8A1702A (SOP 18PIN) SN8A1702A (PDIP 18PIN) SN8A1702A (SSOP 20PIN) P0.0/INT0 RST P1.1 P1.0 VSS P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 2 3 4 5 6 7 8 9 SN8A1702AP SN8A1702AS 18 V D D 17 X I N 16 X O U T 15 P 5 . 0 14 P 5 . 1 13 P 5 . 2 12 P 5 . 3 11 P 5 . 4 / B Z 0 / P W M 0 10 V D D VSS VSS P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 AVREFH VDD P5.3 P5.2 1 U 20 P 1 . 0 2 19 P 1 . 1 3 18 R S T 4 17 P 0 . 0 / I N T 0 5 16 V D D 6 15 X I N 7 14 X O U T 8 13 P 5 . 0 9 12 P 5 . 1 10 11 P 5 . 4 / B Z 0 / P W M 0 SN8A1702AX Only MASK type support SSOP20 package SONiX TECHNOLOGY CO., LTD Page 17 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC OTP Type: SN8P1704 (SOP 28PIN) SN8P1704 (SKDIP 28PIN) P1.4 P1.3 VDD P1.2 P1.1 P1.0 VSS P4.4/AIN4 P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 AVREFH VDD 1U 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 SN8P1704K SN8P1704S RST P0.2/INT2 P0.1/INT1 P0.0/INT0 VDD/VPP XIN XOUT VSS P5.0/SCK P5.1/SI P5.2/SO P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 DAO MASK Type: SN8A1704A (SOP 28PIN) SN8A1704A (SKDIP 28PIN) P1.4 1 U P1.3 2 VDD 3 P1.2 4 P1.1 5 P1.0 6 VSS 7 P4.4/AIN4 8 P4.3/AIN3 9 P4.2/AIN2 10 P4.1/AIN1 11 P4.0/AIN0 12 AVREFH 13 VDD 14 SN8A1704AK SN8A1704AS 28 RST 27 P0.2/INT2 26 P0.1/INT1 25 P0.0/INT0 24 VDD 23 XIN 22 XOUT 21 VSS 20 P5.0/SCK 19 P5.1/SI 18 P5.2/SO 17 P5.3/BZ1/PWM1 16 P5.4/BZ0/PWM0 15 DAO SONiX TECHNOLOGY CO., LTD Page 18 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC OTP Type: SN8P1706 (P-DIP 40PIN) P1.5 P1.4 P1.3 VDD P1.2 P1.1 P1.0 P2.0 P2.1 P2.2 P2.3 VSS P4.7/AIN7 P4.6/AIN6 P4.5/AIN5 P4.4/AIN4 P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 SN8P1706P RST P0.2/INT2 P0.1/INT1 P0.0/INT0 VDD/VPP XIN XOUT VSS P2.4 P5.0/SCK P5.1/SI P5.2/SO P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 P5.5 P5.6 P5.7 DAO VDD AVREFH MASK Type: SN8A1706A (P-DIP 40PIN) P1.5 P1.4 P1.3 VDD P1.2 P1.1 P1.0 P2.0 P2.1 P2.2 P2.3 AVREFL P4.7/AIN7 P4.6/AIN6 P4.5/AIN5 P4.4/AIN4 P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 18 23 19 22 20 21 SN8A1706AP RST P0.2/INT2 P0.1/INT1 P0.0/INT0 NC XIN XOUT VSS P2.4 P5.0/SCK P5.1/SI P5.2/SO P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 P5.5 P5.6 P5.7 DAO VDD AVREFH For OTP type (SN8P1706) compatible issue, please connect AVREFL pin of MASK type (SN8A1706A) to the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage. SONiX TECHNOLOGY CO., LTD Page 19 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC OTP Type: SN8P1707 (QFP 44PIN) P5.3/BZ1/PWM1 P4.4/AIN4 P5.3/BZ1/PWM1 P4.4/AIN4 P5.0/SCK P4.7/AIN7 P5.0/SCK P4.7/AIN7 44 43 42 41 40 39 38 37 36 35 34 VPP/VDD 1 O 33 P5.4/BZ0/PWM0 P0.0/INT0 2 32 P5.5 P0.1/INT1 3 31 P5.6 P0.2/INT2 4 30 P5.7 RST 5 29 DAO P1.5 6 SN8P1707Q 28 VDD P1.4 7 27 AVREFH P1.3 8 26 P4.0/AIN0 VDD 9 25 P4.1/AIN1 P1.2 10 24 P4.2/AIN2 P1.1 11 23 P4.3/AIN3 12 13 14 15 16 17 18 19 20 21 22 VSS AVSS P4.6/AIN6 P4.6/AIN6 P5.1/SI P4.5/AIN5 P4.5/AIN5 P5.2/SO P1.0 P2.0 P2.1 P2.2 P2.3 MASK Type: SN8A1707A (QFP 44PIN) XOUT P2.7 P2.6 P2.5 44 43 42 41 40 39 38 37 36 35 34 NC 1 O 33 P5.4/BZ0/PWM0 P0.0/INT0 2 32 P5.5 P0.1/INT1 3 31 P5.6 P0.2/INT2 4 30 P5.7 RST 5 29 DAO P1.5 6 SN8A1707AQ 28 VDD P1.4 7 27 AVREFH P1.3 8 26 P4.0/AIN0 VDD 9 25 P4.1/AIN1 P1.2 10 24 P4.2/AIN2 P1.1 11 23 P4.3/AIN3 12 13 14 15 16 17 18 19 20 21 22 VSS AVREFL P1.0 P2.0 P2.1 P2.2 P2.3 For OTP type (SN8P1707) compatible issue, please connect AVREFL pin of MASK type (SN8A1707A) to the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage. P2.4 VSS XIN P5.2/SO P5.1/SI XOUT P2.7 P2.6 P2.5 P2.4 VSS XIN SONiX TECHNOLOGY CO., LTD Page 20 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC OTP Type: SN8P1708 (SSOP 48PIN) SN8P1708 (P-DIP 48PIN) P2.5 P2.6 P2.7 VSS VSS XOUT XIN VPP/VDD P0.0/INT0 P0.1/INT1 P0.2/INT2 RST P1.5 P1.4 P1.3 VDD VSS P1.2 P1.1 P1.0 P2.0 P2.1 P2.2 P2.3 1 U 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 SN8P1708P SN8P1708X P2.4 P5.0/SCK P5.1/SI P5.2/SO P5.3/BZ1/PWM1 VSS P5.4/BZ0/PWM0 P5.5 P5.6 P5.7 DAO VDD AVDD AVREFH P4.0/AIN0 P4.1/AIN1 P4.2/AIN2 P4.3/AIN3 P4.4/AIN4 P4.5/AIN5 P4.6/AIN6 P4.7/AIN7 AVSS VSS MASK Type: SN8A1708A (SSOP 48PIN) SN8A1708A (P-DIP 48PIN) 1 U 48 P2.4 2 47 P5.0/SCK 3 46 P5.1/SI 4 45 P5.2/SO 5 44 P5.3/BZ1/PWM1 6 43 VSS 7 42 P5.4/BZ0/PWM0 8 41 P5.5 9 40 P5.6 10 39 P5.7 11 38 DAO 12 37 VDD 13 36 AVDD 14 35 AVREFH 15 34 P4.0/AIN0 16 33 P4.1/AIN1 17 32 P4.2/AIN2 18 31 P4.3/AIN3 19 30 P4.4/AIN4 20 29 P4.5/AIN5 21 28 P4.6/AIN6 22 27 P4.7/AIN7 23 26 AVREFL 24 25 VSS SN8A1708AP SN8A1708AX For OTP type (SN8P1708) compatible issue, please connect AVREFL pin of MASK type (SN8A1708A) to the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage. P2.5 P2.6 P2.7 VSS VSS XOUT XIN NC P0.0/INT0 P0.1/INT1 P0.2/INT2 RST P1.5 P1.4 P1.3 VDD VSS P1.2 P1.1 P1.0 P2.0 P2.1 P2.2 P2.3 SONiX TECHNOLOGY CO., LTD Page 21 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PIN DESCRIPTIONS PIN NAME VDD, VSS AVDD, AVSS VPP/VDD RST XIN, XOUT P0.0 / INT0 P0.1 / INT1 P0.2 / INT2 P1.0 ~ P1.5 P2.0 ~ P2.7 P4.0 ~ P4.7 P5.0 / SCK P5.1 / SI P5.2 / SO P5.3 / BZ1 / PWM1 P5.4 / BZ0 / PWM0 P5.5 ~ P5.7 AVREFH AIN0 ~ AIN7 DAO TYPE P P P I I, O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O DESCRIPTION Power supply input pins for digital circuit. Power supply input pins for analog circuit. OTP ROM programming pin. Connect to VDD in normal operation. System reset input pin. Schmitt trigger structure, active "low", normal stay to "high". External oscillator pins. RC mode from XIN. Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resisters. Port 0.1 and shared with INT1 trigger pin (Schmitt trigger) / Built-in pull-up resisters. Port 0.2 and shared with INT2 trigger pin (Schmitt trigger) / Built-in pull-up resisters. Port 1.0~Port 1.5 bi-direction pins / Built-in pull-up resisters. Port 2.0~Port 2.7 bi-direction pins / Built-in pull-up resisters. Port 4.0~Port 4.7 bi-direction pins / Built-in pull-up resisters. Port 5.0 bi-direction pin and SIO's clock input/output / Built-in pull-up resisters. Port 5.1 bi-direction pin and SIO's data input / Built-in pull-up resisters. Port 5.2 bi-direction pin and SIO's data output / Built-in pull-up resisters. Port 5.3 bi-direction pin, TC1 / 2 signal output pin for buzzer or PWM1 output pin. Built-in pull-up resisters. Port 5.4 bi-direction pin, TC0 / 2 signal output pin for buzzer or PWM0 output pin. Built-in pull-up resisters. Port 5.5~Port 5.7 bi-direction pins / Built-in pull-up resisters. A/D converter high analog reference voltage. Analog signal input pins for ADC converter. 5-bit DAC signal output pin. Table 1-4. SN8P1700 Pin Description PIN CIRCUIT DIAGRAMS Port1, 2, 4, 5 structure Port0 structure PUR PUR PnM PnM Pin Pin Int. bus PnM Latch Int. bus Figure 1-2. Pin Circuit Diagram Note: All of the latch output circuits are push-pull structures. SONiX TECHNOLOGY CO., LTD Page 22 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 2 CODE OPTION TABLE Code Option Content RC 32K X'tal 12M X'tal 4M X'tal Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable High_Clk High_Clk / 2 OSG Watch_Dog LVD Security Function Description Low cost RC for external high clock oscillator Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator High speed crystal /resonator (e.g. 12M) for external high clock oscillator Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator External high clock divided by two, Fosc = high clock / 2 Fosc = high clock Enable Oscillator Safe Guard function Disable Oscillator Safe Guard function Enable Watch Dog function Disable Watch Dog function Enable the low voltage detect Disable the low voltage detect Enable ROM code Security function Disable ROM code Security function Table 2-1. Code Option Table of SN8P1700 Notice : The OSG working voltage and the frequency relation table: The min. working voltage will be affect by the OSG option. It is very important to check this code option. Turn on the OSG will improve the EMI performance. But the side effect is an increase in the working voltage. OSC. Freq.(Mhz) OSG ON (Volt) 1 2 4 6 8 10 12 16 18 20 2.4 2.4 2.5 2.5 2.6 2.8 3 3.5 3.7 4.1 OSG OFF(Volt) 2.2 2.2 2.2 2.3 2.4 2.6 2.7 2.8 3 3.2 Notice : The system working frequency is only warranty under 16Mhz. SONiX TECHNOLOGY CO., LTD Page 23 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 3 ADDRESS SPACES PROGRAM MEMORY (ROM) OVERVIEW ROM Maps for SN8P1700 devices provide OTP memory that programmable by user. SN8P1702 has 1K x 16-bit program memory, SN8P1704 has 2K x 16-bit program memory and SN8P1706, SN8P1707 and SN8P1708 have 4K x 16-bit program memory. The SN8P1700 program memory is able to fetch instructions through 12-bit wide PC (Program Counter) and can look up ROM data by using ROM code registers (R, X, Y, Z). In standard configuration, the device's 4,096 x 16-bit program memory has four areas: 1-word reset vector addresses 1-word Interrupt vector addresses 5-words reserved area 4K words (SN8P1706, SN8P1707, SN8P1708) 2K words (SN8P1704) 1K words (SN8P1702) All of the program memory is partitioned into three coding areas. The 1st area is located from 00H to 03H(The Reset vector area), the 2nd area is a reserved area 04H ~07H, the 3rd area is for the interrupt vector and the user code area from 0008H to 0FFEH. The address 08H is the interrupt enter address point. ROM Reset vector General purpose area 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H . . 000FH 0010H 0011H . . 03FEH 03FFH User reset vector Jump to user start address Jump to user start address Jump to user start address Reserved Interrupt vector User interrupt vector User program General purpose area End of user program Reserved Figure 3-1. ROM Address Structure (SN8P1702) SONiX TECHNOLOGY CO., LTD Page 24 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H . . 000FH 0010H 0011H . . 07FEH 07FFH ROM Reset vector General purpose area User reset vector Jump to user start address Jump to user start address Jump to user start address Reserved Interrupt vector User interrupt vector User program General purpose area End of user program Reserved Figure 3-2. ROM Address Structure (SN8P1704) 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H . . 000FH 0010H 0011H . . 0FFEH 0FFFH ROM Reset vector General purpose area User reset vector Jump to user start address Jump to user start address Jump to user start address Reserved Interrupt vector User interrupt vector User program General purpose area End of user program Reserved Figure 3-3. ROM Address Structure (SN8P1706/SN8P1707/SN8P1708) SONiX TECHNOLOGY CO., LTD Page 25 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC USER RESET VECTOR ADDRESS (0000H) A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory. Example: After power on reset, external reset active or reset by watchdog timer overflow. CHIP SN8P1708 ORG JMP . ORG START: . . . . ENDP 0 START 10H ; 0010H, The head of user program. ; User program ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved ; End of program INTERRUPT VECTOR ADDRESS (0008H) A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory. Example 1: This demo program includes interrupt service routine and the user program is behind the interrupt service routine. CHIP SN8P1708 ORG JMP . ORG B0XCH PUSH . . . POP B0XCH RETI START: . . . . JMP 0 START 8 A, ACCBUF ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved ; Interrupt service routine ; B0XCH doesn't change C, Z flag ; Push 80H ~ 87H system registers ; Pop 80H ~ 87H system registers A, ACCBUF ; End of interrupt service routine ; The head of user program. ; User program START ; End of user program ENDP ; End of program SONiX TECHNOLOGY CO., LTD Page 26 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example 2: The demo program includes interrupt service routine and the address of interrupt service routine is in a special address of general-purpose area. CHIP SN8P1708 ORG JMP . ORG JMP ORG START: . . . . JMP MY_IRQ: B0XCH PUSH . . . POP B0XCH RETI ENDP A, ACCBUF 0 START 08 MY_IRQ 10H ; 0010H, The head of user program. ; User program ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved ; 0008H, Jump to interrupt service routine address START ; End of user program ;The head of interrupt service routine ; B0XCH doesn't change C, Z flag ; Push 80H ~ 87H system registers ; Pop 80H ~ 87H system registers A, ACCBUF ; End of interrupt service routine ; End of program Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are as following. 1. The address 0000H is a "JMP" instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and necessary. 2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H (Example1) or to put a "JMP" instruction in 0008H then place the interrupt service routine in other general-purpose ROM area (Example2) to get more modularized coding style. SONiX TECHNOLOGY CO., LTD Page 27 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC CHECKSUM CALCULATION The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value. Example: The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of user's code MOV A,#END_USER_CODE$L B0MOV END_ADDR1,A ;save low end address to end_addr1 MOV A,#END_USER_CODE$ M B0MOV END_ADDR2,A ;save middle end address to end_addr2 CLR Y ;set Y to ooH CLR Z ;set Z to 00H @@: CALL MOVC B0BSET ADD MOV ADC JMP AAA: INCMS JMP JMP END_CHECK: MOV CMPRS JMP MOV CMPRS JMP JMP YZ_CHECK: MOV CMPRS RET MOV CMPRS RET INCMS INCMS INCMS INCMS RET Y_ADD_1: INCMS NOP JMP CHECKSUM_END: .......... .......... END_USER_CODE: ;Label of program end Y @B ;increase Y ;jump to checksum calculate A,#04H A,Z A,#00H A,Y Z Z Z Z A,END_ADDR1 A,Z AAA A,END_ADDR2 A,Y AAA CHECKSUM_END ;check if Z = low end address ;if Not jump to checksum calculate ;if Yes, check if Y = middle end address ;if Not jump to checksum calculate ;if Yes checksum calculated is done. ;check if YZ=0004H ;check if Z=04H ;if Not return to checksum calculate ;if Yes, check if Y=00H ;if Not return to checksum calculate ;if Yes, increase 4 to Z Z @B Y_ADD_1 ;Z=Z+1 ;if Z!= 00H calculate to next address ;if Z=00H increase Y YZ_CHECK FC DATA1,A A,R DATA2,A END_CHECK ;call function of check yz value ; ;clear C glag ;add A to Data1 ;add R to Data2 ;check if the YZ address = the end of code ;set YZ=0008H then return SONiX TECHNOLOGY CO., LTD Page 28 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC GENERAL PURPOSE PROGRAM MEMORY AREA The 40891-word at ROM locations 0010H~0FFEH are used as general-purpose memory. The area is stored instruction's op-code and look-up table data. The SN8P1700 includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, X, Y, Z). The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can't leap over the boundary by program counter automatically. Users need to modify the PCH value to "PCH+1" as the PCL overflow (from 0FFH to 000H). Notice: 1:The SN8P1702's ROM size is about 1K words and the SN8P1704's ROM size is about 2K words. LOOKUP TABLE DESCRIPTION In the ROM's data lookup function, the X register is pointed to the highest 8-bit, Y register to the middle 8-bit and Z register to the lowest 8-bit data of ROM address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data stored in R register. Example: To look up the ROM data located "TABLE1". B0MOV B0MOV MOVC Y, #TABLE1$M Z, #TABLE1$L INCMS JMP INCMS NOP @@: TABLE1: MOVC . DW DW DW Z @F Y . 0035H 5105H 2012H ; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; ; Increment the index address for next address ; Z+1 ; Not overflow ; Z overflow (FFH 00), Y=Y+1 ; Not overflow ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data. ;" ;" CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users can omit "B0MOV X, #TABLE1$H". SONiX ICE support more larger program memory addressing capability. So make sure X register is "0" to avoid unpredicted error in loop-up table operation. Example: INC_YZ Macro INC_YZ MACRO INCMS JMP INCMS NOP @@: ENDM Z @F Y ; Z+1 ; Not overflow ; Y+1 ; Not overflow SONiX TECHNOLOGY CO., LTD Page 29 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer following example for detailed information: Example: Increase Y and Z register by B0ADD/ADD instruction B0MOV B0MOV B0MOV B0ADD B0BTS1 JMP INCMS NOP GETDATA: MOVC Y, #TABLE1$M Z, #TABLE1$L A, BUF Z, A FC GETDATA Y ; To set lookup table's middle address. ; To set lookup table's low address. ; Z = Z + BUF. ; Check the carry flag. ; FC = 0 ; FC = 1. Y+1. TABLE1: . DW DW DW . 0035H 5105H 2012H ; ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . ; ; To define a word (16 bits) data. ;" ;" SONiX TECHNOLOGY CO., LTD Page 30 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC JUMP TABLE DESCRIPTION The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way is easy to make a multi-stage program. When carry flag occurs after executing of "ADD PCL, A", it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words. Example : If PC = 0323H ORG B0ADD JMP JMP JMP JMP (PCH = 03HPCL = 23H) 0X0100 PCL, A A0POINT A1POINT A2POINT A3POINT ; The jump table is from the head of the ROM boundary ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H). Example: If "jump table" crosses over ROM boundary will cause errors. ROM Address . . . 0X00FD 0X00FE 0X00FF 0X0100 0X0101 . . . . . B0ADD JMP JMP JMP JMP . . PCL, A A0POINT A1POINT A2POINT A3POINT ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0 ; ACC = 1 ; ACC = 2 jump table cross boundary here ; ACC = 3 SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro is maybe wasting some ROM size. Notice the maximum jmp table number for this macro is limited under 254. @JMP_A MACRO IF JMP ORG ENDIF ADD ENDM VAL (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) ($ | 0XFF) ($ | 0XFF) PCL, A Note: "VAL" is the number of the jump table listing number. SONiX TECHNOLOGY CO., LTD Page 31 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: "@JMP_A" application in SONIX macro file called "MACRO3.H". B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT If the jump table position is from 00FDH to 0101H, the "@JMP_A" macro will make the jump table to start from 0100h. SONiX TECHNOLOGY CO., LTD Page 32 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC DATA MEMORY (RAM) OVERVIEW The SN8P1700 has internally built-in the data memory up to 256 bytes for storing the general-purpose data. For SN8P1702 48 * 8-bit general purpose area in bank 0 128 * 8-bit system special register area For SN8P1704 128 * 8-bit general purpose area in bank 0 128 * 8-bit system special register area For SN8P1706/SN8P1707/SN8P1708 128 * 8-bit general purpose area in bank 0 128 * 8-bit general purpose area in bank 1 128 * 8-bit system special register area The memory is separated into bank 0 and bank 1. The user can program RAM bank selection bits of RBANK register to access all data in any of the two RAM banks. The bank 0, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register. The bank 1, using the first 128-byte location assigned as general-purpose area, and others useless. RAM location 000h " " " " " 03Fh 080h " " " " " 0FFh 000h~03Fh of Bank 0 = To store generalpurpose data (64 bytes). General purpose area BANK 0 080h~0FFh of Bank 0 = To store system registers (128 bytes). System register End of bank 0 area Figure 3-4. RAM Location of SN8P1702 SONiX TECHNOLOGY CO., LTD Page 33 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC RAM location 000h " " " " " 07Fh 080h " " " " " 0FFh 000h~03Fh of Bank 0 = To store generalpurpose data (128 bytes). General purpose area BANK 0 080h~0FFh of Bank 0 = To store system registers (128 bytes). System register End of bank 0 area Figure 3-5. RAM Location of SN8P1704 RAM location 000h " " " " " 07Fh 080h " " " " " 0FFh 100h " " " " 17Eh 17Fh 000h~07Fh of Bank 0 = To store generalpurpose data (128 bytes). General purpose area BANK 0 080h~0FFh of Bank 0 = To store system registers (128 bytes). System register End of bank 0 area Bank 1 = To store general-purpose data. General purpose area BANK 1 End of bank 1 area Bank 1 has 128 bytes RAM. Figure 3-6 RAM Location of SN8P1706/SN8P1707/SN8P1708 Note: The undefined locations of system register area are logic "high" after executing read instruction "MOV A, M". SONiX TECHNOLOGY CO., LTD Page 34 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC RAM BANK SELECTION The RBANK is a 1-bit register located at 87H in RAM bank 0. The user can access RAM data by using this register pointing to working RAM bank for ACC to read/write RAM data. RBANK initial value = xxxx xxx0 087H RBANK Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 RBNKS0 R/W RBNKSn: RAM bank selecting control bit. 0 = bank 0, 1 = bank 1. Example: RAM bank selecting. ; BANK 0 CLR . ; BANK 1 MOV B0MOV . A, #1 RBANK, A ; b0bset FRBNKS0 RBANK ; b0bclr FRBNKS0 Note: "B0MOV" instruction can access the RAM of bank 0 in other bank situation directly. Example: Access RAM bank 0 in RAM bank 1. ; BANK 1 B0BSET B0MOV MOV . . MOV B0MOV RBNKS0 A, BUF0 BUF1, A . A, BUF1 BUF0, A ; Get into RAM bank 1 ; Read BUF0 data. BUF0 is in RAM bank0. ; Write BUF0 data to BUF1. BUF1 is in RAM bank1. ; Read BUF1(bank1) data and store in ACC. ; Write ACC data to BUF0(bank0). Under bank 1 situation, using "B0MOV" instruction is an easy way to access RAM bank 0 data. User can make a habit to read/write system register (0087H~00FFH). Then user can access system registers without switching RAM bank. Example: To Access the system registers in bank 1 situation. ; BANK 1 B0BSET . MOV B0MOV . B0MOV MOV RBNKS0 . A, #0FFH P1, A A, P0 BUF1, A ; Switch the Ram Bank into bank 1 ; Set all pins of P1 to be logic high. ; Operate the bank 0 special register by the b0mov instruction ; while the RAM system in the bank1. ; Read P0 data in the Bank 0 and store into BUF1 in the bank 1. ; SONiX TECHNOLOGY CO., LTD Page 35 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC WORKING REGISTERS The locations 80H to 85H of RAM bank 0 in data memory stores the specially defined registers such as register H, L, R, X, Y, Z, respectively shown in the following table. These registers can use as the general purpose of working buffer and be used to access ROM's and RAM's data. For instance, all of the ROM's table can be looked-up with R, X, Y and Z registers. The data of RAM memory can be indirectly accessed with H, L, Y and Z registers. RAM 80H L R/W 81H H R/W 82H R R/W 83H Z R/W 84H Y R/W 85H X R/W H, L REGISTERS The H and L are 8-bit register with two major functions. One is to use the registers as working register. The other is to use the registers as data pointer to access RAM's data. The @HL that is data point_0 index buffer located at address E6H in RAM bank_0. It employs H and L registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of H register is pointed to RAM bank number and L register is pointed to RAM address number, respectively. The higher 4-bit data of H register is truncated in RAM indirectly access mode. H initial value = 0000 0000 081H H Bit 7 HBIT7 R/W Bit 6 HBIT6 R/W Bit 5 HBIT5 R/W Bit 4 HBIT4 R/W Bit 3 HBIT3 R/W Bit 2 HBIT2 R/W Bit 1 HBIT1 R/W Bit 0 HBIT0 R/W L initial value = 0000 0000 080H L Bit 7 LBIT7 R/W Bit 6 LBIT6 R/W Bit 5 LBIT5 R/W Bit 4 LBIT4 R/W Bit 3 LBIT3 R/W Bit 2 LBIT2 R/W Bit 1 LBIT1 R/W Bit 0 LBIT0 R/W Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to access data as following. B0MOV B0MOV B0MOV H, #00H L, #20H A, @HL ; To set RAM bank 0 for H register ; To set location 20H for L register ; To read a data into ACC Example: Clear general-purpose data memory area of bank 0 using @HL register. CLR MOV B0MOV CLR_HL_BUF: CLR DECMS JMP CLR END_CLR: . . . . Page 36 @HL L CLR_HL_BUF @HL ; End of clear general purpose data memory area of bank 0 ; Clear @HL to be zero ; L - 1, if L = 0, finish the routine ; Not zero H A, #07FH L, A ; H = 0, bank 0 ; L = 7FH, the last address of the data memory area SONiX TECHNOLOGY CO., LTD Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Y, Z REGISTERS The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third, the registers can be address ROM location in order to look-up ROM data. Y initial value = 0000 0000 084H Y Bit 7 YBIT7 R/W Bit 6 YBIT6 R/W Bit 5 YBIT5 R/W Bit 4 YBIT4 R/W Bit 3 YBIT3 R/W Bit 2 YBIT2 R/W Bit 1 YBIT1 R/W Bit 0 YBIT0 R/W Z initial value = 0000 0000 083H Z Bit 7 ZBIT7 R/W Bit 6 ZBIT6 R/W Bit 5 ZBIT5 R/W Bit 4 ZBIT4 R/W Bit 3 ZBIT3 R/W Bit 2 ZBIT2 R/W Bit 1 ZBIT1 R/W Bit 0 ZBIT0 R/W The @YZ that is data point_1 index buffer located at address E7H in RAM bank 0. It employs Y and Z registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of Y register is pointed to RAM bank number and Z register is pointed to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly access mode. Example: If want to read a data from RAM address 25H of bank 1, it can use indirectly addressing mode to access data as following. B0MOV B0MOV B0MOV Y, #01H Z, #25H A, @YZ ; To set RAM bank 1 for Y register ; To set location 25H for Z register ; To read a data into ACC Example: Clear general-purpose data memory area of bank 1 using @YZ register. MOV B0MOV MOV B0MOV CLR_YZ_BUF: CLR DECMS JMP CLR END_CLR: . Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about Y, Z register look-up table application. @YZ Z CLR_YZ_BUF @YZ ; End of clear general purpose data memory area of bank 0 ; Clear @YZ to be zero ; Y - 1, if Y= 0, finish the routine ; Not zero A, #1 Y, A A, #07FH Z, A ; Y = 1, bank 1 ; Y = 7FH, the last address of the data memory area SONiX TECHNOLOGY CO., LTD Page 37 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC X REGISTERS There are two major functions of the X register. First, X register can be used as working registers. Second, the X registers must be clear in order to look-up the ROM data. The SN8P1700's program counter only has 12-bit. In look-up table function, the users can omit X register. X initial value = 0000 0000 085H X Bit 7 XBIT7 R/W Bit 6 XBIT6 R/W Bit 5 XBIT5 R/W Bit 4 XBIT4 R/W Bit 3 XBIT3 R/W Bit 2 XBIT2 R/W Bit 1 XBIT1 R/W Bit 0 XBIT0 R/W Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about X register look-up table application. R REGISTERS There are two major functions of the R register. First, R register can be used as working registers. Second, the R registers can be store high-byte data of look-up ROM data. After MOVC instruction executed, the high-byte data of a ROM address will be stored in R register and the low-byte data stored in ACC. R initial value = 0000 0000 082H R Bit 7 RBIT7 R/W Bit 6 RBIT6 R/W Bit 5 RBIT5 R/W Bit 4 RBIT4 R/W Bit 3 RBIT3 R/W Bit 2 RBIT2 R/W Bit 1 RBIT1 R/W Bit 0 RBIT0 R/W Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about R register look-up table application. SONiX TECHNOLOGY CO., LTD Page 38 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PROGRAM FLAG The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register. PFLAG initial value = xxxx x000 086H PFLAG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C R/W Bit 1 DC R/W Bit 0 Z R/W CARRY FLAG C = 1: If executed arithmetic addition with occurring carry signal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic "1". C = 0: If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with borrowing signal or executed rotation instruction with shifting out logic "0". DECIMAL CARRY FLAG DC = 1: If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction without borrow signal from high nibble. DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction with borrow signal from high nibble. ZERO FLAG Z = 1: After operation, the content of ACC is zero. Z = 0: After operation, the content of ACC is not zero. SONiX TECHNOLOGY CO., LTD Page 39 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ACCUMULATOR The ACC is an 8-bits data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can't be access by "B0MOV" instruction during the instant addressing mode. Example: Read and write ACC value. ; Read ACC data and store in BUF data memory MOV . BUF, A . ; Write a immediate data into ACC MOV . A, #0FH . ; Write ACC data from BUF data memory MOV . A, BUF . The PUSH and POP instructions don't store ACC value as any interrupt service executed. ACC must be exchanged to another data memory defined by users. Thus, once interrupt occurs, these data must be stored in the data memory based on the user's program as follows. Example: ACC and working registers protection. ACCBUF INT_SERVICE: B0XCH PUSH. . . . POP B0XCH RETI A, ACCBUF . . ; B0XCH doesn't change C, Z flag ; Push instruction EQU 00H ; ACCBUF is ACC data buffer in bank 0. ; Pop instruction A, ACCBUF ; Re-load ACC ; Exit interrupt service vector Notice: To save and re-load ACC data must be used "B0XCH" instruction, or the PLAGE value maybe modified by ACC. SONiX TECHNOLOGY CO., LTD Page 40 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC STACK OPERATIONS OVERVIEW The stack buffer of SN8P1700 has 8-level high area and each level is 12-bits length. This buffer is designed to save and restore program counter's (PC) data when interrupt service is executed. The STKP register is a pointer designed to point active level in order to save or restore data from stack buffer for kernel circuit. The STKnH and STKnL are the 12-bit stack buffers to store program counter (PC) data. STACK BUFFER PCH PCL RET / RETI CALL / interrupt STKP = 7 STKP = 6 STKP = 5 STKP = 4 STKP STK3H STK4H STK5H STK6H STK7H STK0H STK1H STK2H STKP STK3L STK4L STK5L STK6L STK7L STK0L STK1L STK2L STKP + 1 STKP - 1 STKP = 3 STKP = 2 STKP = 1 STKP = 0 Figure 3-7 Stack-Save and Stack-Restore Operation SONiX TECHNOLOGY CO., LTD Page 41 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC STACK REGISTERS The stack pointer (STKP) is a 4-bit register to store the address used to access the stack buffer, 12-bits data memory (STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the top of the stack (Stack-Save) and reading (Stack-Restore) from the top of stack. Stack-Save operation decrements the STKP and the Stack-Resotre operation increments one time. That makes the STKP always points to the top address of stack buffer and writes the last program counter value (PC) into the stack buffer. The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0. STKP (stack pointer) initial value = 0xxx 1111 0DFH STKP Bit 7 GIE R/W Bit 6 Bit 5 Bit 4 Bit 3 STKPB3 R/W Bit 2 STKPB2 R/W Bit 1 STKPB1 R/W Bit 0 STKPB0 R/W STKPBn: Stack pointer. (n = 0 ~ 3) GIE: Global interrupt control bit. 0 = disable, 1 = enable. More detail information is in interrupt chapter. Example: Stack pointer (STKP) reset routine. MOV B0MOV A, #00001111B STKP, A STKn = STKnH + STKnL (n = 7 ~ 0) Bit 3 SnPC11 R/W Bit 2 SnPC10 R/W Bit 1 SnPC9 R/W Bit 0 SnPC8 R/W STKn (stack buffer) initial value = xxxx xxxx xxxx xxxx, 0F0H~0FFH STKnH Bit 7 Bit 6 Bit 5 - Bit 4 - 0F0H~0FFH STKnL Bit 7 SnPC7 R/W Bit 6 SnPC6 R/W Bit 5 SnPC5 R/W Bit 4 SnPC4 R/W Bit 3 SnPC3 R/W Bit 2 SnPC2 R/W Bit 1 SnPC1 R/W Bit 0 SnPC0 R/W STKnH: Store PCH data as interrupt or call executing. The n expressed 0 ~7. STKnL: Store PCL data as interrupt or call executing. The n expressed 0 ~7. SONiX TECHNOLOGY CO., LTD Page 42 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC STACK OPERATION EXAMPLE The two kinds of Stack-Save operations to reference the stack pointer (STKP) and write the program counter contents (PC) into the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP is decremented and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as following table. Stack Level 0 1 2 3 4 5 6 7 >8 STKP Register STKPB2 STKPB1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 - STKPB3 1 1 1 1 1 1 1 1 - STKPB0 1 0 1 0 1 0 1 0 - Stack Buffer High Byte Low Byte STK0H STK1H STK2H STK3H STK4H STK5H STK6H STK7H STK0L STK1L STK2L STK3L STK4L STK5L STK6L STK7L - Description Stack Overflow Table 3-1. STKP, STKnH and STKnL relative of Stack-Save Operation There is a Stack-Restore operation corresponding each push operation to restore the program counter (PC). The RETI instruction is for interrupt service routine. The RET instruction is for CALL instruction. When a Stack-Restore operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as following table. Stack Level 7 6 5 4 3 2 1 0 STKP Register STKPB2 STKPB1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 STKPB3 1 1 1 1 1 1 1 1 STKPB0 0 1 0 1 0 1 0 1 Stack Buffer High Byte Low Byte STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L Description - Table 3-2. STKP, STKnH and STKnL relative of Stack-Restore Operation SONiX TECHNOLOGY CO., LTD Page 43 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PROGRAM COUNTER The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 bits and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution. Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 11. PC Initial value = xxxx 0000 0000 0000 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 0 0 PCH Bit 8 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 0 0 PCL Bit 2 0 Bit 1 0 Bit 0 0 PC PCH Initial value = xxxx 0000 0CFH PCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PC11 R/W Bit 2 PC10 R/W Bit 1 PC9 R/W Bit 0 PC8 R/W PCL Initial value = 0000 0000 0CEH PCL Bit 7 PC7 R/W Bit 6 PC6 R/W Bit 5 PC5 R/W Bit 4 PC4 R/W Bit 3 PC3 R/W Bit 2 PC2 R/W Bit 1 PC1 R/W Bit 0 PC0 R/W SONiX TECHNOLOGY CO., LTD Page 44 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ONE ADDRESS SKIPPING There are 9 instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is matched, the PC will add 2 steps to skip next instruction. If the condition of bit test instruction is matched, the PC will add 2 steps to skip next instruction. B0BTS1 JMP . NOP B0MOV B0BTS0 JMP . NOP FC C0STEP ; Skip next instruction, if Carry_flag = 1 ; Else jump to C0STEP. C0STEP: A, BUF0 FZ C1STEP ; Move BUF0 value to ACC. ; Skip next instruction, if Zero flag = 0. ; Else jump to C1STEP. C1STEP: If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS JMP . NOP A, #12H C0STEP ; Skip next instruction, if ACC = 12H. ; Else jump to C0STEP. C0STEP: If the result after increasing or decreasing by 1 is 0xFF or 0x00, the PC will add 2 steps to skip next instruction. INCS instruction: INCS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. C0STEP: INCMS instruction: INCMS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. C0STEP: DECS instruction: DECS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. C0STEP: DECMS instruction: DECMS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. C0STEP: SONiX TECHNOLOGY CO., LTD Page 45 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC MULTI-ADDRESS JUMPING Users can jump round multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. If carry signal occurs after execution of ADD PCL, A, the carry signal will not affect PCH register. Example: If PC = 0323H ; PC = 0323H MOV B0MOV . . . MOV B0MOV (PCH = 03HPCL = 23H) ; PC = 0328H A, #28H PCL, A . . . A, #00H PCL, A ; Jump to address 0328H ; Jump to address 0300H Example: If PC = 0323H ; PC = 0323H B0ADD JMP JMP JMP JMP . (PCH = 03HPCL = 23H) PCL, A A0POINT A1POINT A2POINT A3POINT . ; PCL = PCL + ACC, the PCH cannot be changed. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; SONiX TECHNOLOGY CO., LTD Page 46 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 4 ADDRESSING MODE OVERVIEW The SN8P1700 provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. The main purpose of the three different modes is described in the following: IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location (MOV A, #I, B0MOV M,#I) in ACC or specific RAM. Immediate addressing mode MOV A, #12H ; To set an immediate data 12H into ACC DIRECTLY ADDRESSING MODE The directly addressing mode uses address number to access memory location (MOV A,12H, MOV 12H,A). Directly addressing mode B0MOV A, 12H ; To get a content of location 12H of bank 0 and save in ACC INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to set up an address in data pointer registers (Y/Z) and uses MOV instruction to read/write data between ACC and @YZ register (MOV A,@YZ, MOV @YZ,A). Example: Indirectly addressing mode with @YZ register CLR B0MOV B0MOV Y Z, #12H A, @YZ ; To clear Y register to access RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. MOV B0MOV B0MOV B0MOV A, #01H Y, A Z, #12H A, @YZ ; To set Y = 1 for accessing RAM bank 1. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. MOV B0MOV B0MOV B0MOV A, #0FH Y, A Z, #12H A, @YZ ; To set Y = 15 for accessing RAM bank 15. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location 012H ; Into ACC. SONiX TECHNOLOGY CO., LTD Page 47 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TO ACCESS DATA in RAM BANK 0 In the RAM bank 0, this area memory can be read/written by these three access methods. Example 1: To use RAM bank0 dedicate instruction (Such as B0xxx instruction). B0MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC Example 2: To use directly addressing mode (Through RBANK register). B0MOV MOV RBANK, #00H A, 12H ; To set RAM bank = 0 ; To move content from location 12H of RAM bank 0 to ACC Example 3: To use indirectly addressing mode with @YZ register. CLR B0MOV B0MOV Y Z, #12H A, @YZ ; To clear Y register for accessing RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. TO ACCESS DATA in RAM BANK 1 In the RAM bank 1, this area memory can be read/written by these two access methods. Example 1: To use directly addressing mode (Through RBANK register). B0MOV MOV RBANK, #01H A, 12H ; To set RAM bank = 1 ; To move content from location 12H of RAM bank 0 to ACC Example 2: To use indirectly addressing mode with @YZ register. MOV B0MOV B0MOV B0MOV A, #01H Y, A Z, #12H A, @YZ ; To set Y = 1 for accessing RAM bank 1. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. SONiX TECHNOLOGY CO., LTD Page 48 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 5 SYSTEM REGISTER OVERVIEW The system special register is located at 80h~FFh. The main purpose of system registers is to control the peripheral hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, timers and counters by programming. The Memory map provides an easy and quick reference source for writing application program. To accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV, B0BSET, B0BCLR...). SYSTEM REGISTER ARRANGEMENT (BANK 0) BYTES of SYSTEM REGISTER SN8P1702 0 8 9 A B C D E F P1W P0 STK7 1 ADM P1M P1 STK7 2 R ADB STK6 3 Z ADR STK6 4 Y P4M P4 STK5 5 P5M P5 STK5 6 PFLAG STK4 7 @YZ STK4 8 STK3 9 STK3 A OSCM TC0M STK2 B TC0C STK2 C STK1 D TC0R STK1 E PCL STK0 F PCH STKP STK0 INTRQ INTEN Table 5-1. System Register Arrangement of SN8P1702 SN8P1704 0 8 9 A B C D E F DAM P1W P0 STK7 1 ADM P1M P1 STK7 2 R ADB STK6 3 Z ADR STK6 4 Y SIOM P4M P4 STK5 5 SIOR P5M P5 STK5 6 PFLAG SIOB STK4 7 @YZ STK4 8 STK3 9 STK3 A OSCM TC0M STK2 B TC0C STK2 C TC1M STK1 D TC0R TC1C STK1 E PCL TC1R STK0 F PCH STKP STK0 INTRQ INTEN Table 5-2. System Register Arrangement of SN8P1704 SONiX TECHNOLOGY CO., LTD Page 49 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1706/SN8P1707/SN8P1708 0 8 9 A B C D E F L DAM P1W P0 - 1 H ADM P1M P1 - 2 R ADB P2M P2 - 3 Z ADR - 4 Y SIOM P4M P4 - 5 X SIOR P5M P5 - 6 SIOB @HL 7 @YZ 8 T0M - 9 T0C - A OSCM TC0M - B TC0C - C TC1M - D TC0R TC1C - E PCL TC1R - F PCH STKP - PFLAG RBANK INTRQ INTEN STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H Table 5-3. System Register Arrangement of SN8P1706/SN8P1707/SN8P1708 Description L, H = X= PFLAG = DAM = ADB = SIOM = SIOB = PnM = INTRQ = OSCM = T0M = T0C = TC1M = TC1C = STKP = @HL = Working & @HL addressing register. Working and ROM address register. ROM page and special flag register. DAC's mode register. ADC's data buffer. SIO mode control register. SIO's data buffer. Port n input/output mode register. Interrupts' request register. Oscillator mode register. Timer 0 mode register. Timer 0 counting register. Timer/Counter 1 mode register. Timer/Counter 1 counting register. Stack pointer buffer. RAM HL indirect addressing index pointer. R= Y, Z = RBANK = ADM = ADR = SIOR = P1W = Pn = INTEN = PCH, PCL = TC0M = TC0C = TC0R = TC1R = STK0~STK7 = @YZ = Working register and ROM lookup data buffer. Working, @YZ and ROM addressing register. RAM Bank Select register. ADC's mode register. ADC's resolution selects register. SIO's clock reload buffer. Port 1 wakeup register. Port n data buffer. Interrupts' enable register. Program counter. Timer/Counter 0 mode register. Timer/Counter 0 counting register. Timer/Counter 0 auto-reload data buffer. Timer/Counter 1 auto-reload data buffer. Stack 0 ~ stack 7 buffer. RAM YZ indirect addressing index pointer. Note: a). All of register names had been declared in SONiX 8-bit MCU assembler. b). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. c). It will get logic "H" data, when use instruction to check empty location. d). The low nibble of ADR register is read only. e). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. SONiX TECHNOLOGY CO., LTD Page 50 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC BITS of SYSTEM REGISTER SN8P1702 System register table Address 082H 083H 084H 086H 0B1H 0B2H 0B3H 0C0H 0C1H 0C4H 0C5H 0C8H 0C9H 0CAH 0CDH 0CEH 0CFH 0D0H 0D1H 0D4H 0D5H 0DAH 0DBH 0DFH 0E7H 0F0H 0F1H 0F2H 0F3H " " " 0FCH 0FDH 0FEH 0FFH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 C DC Z ADENB ADS EOC GCHS 0 CHS1 CHS0 ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 0 0 0 0 0 0 P11W P10W 0 0 0 0 0 0 P11M P10M 0 0 0 0 P43M P42M P41M P40M 0 0 0 P54M P53M P52M P51M P50M 0 0 TC0IRQ 0 0 0 0 P00IRQ 0 0 TC0IEN 0 0 0 0 P00IEN 0 WDRST WDRate 0 CPUM0 CLKMD STPHX 0 TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC10 PC9 PC8 P00 P11 P10 P43 P42 P41 P40 P54 P53 P52 P51 P50 TC0ENB TC0rate2 TC0rate1 TC0rate0 0 ALOAD0 TC0OUT PWM0OUT TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 GIE STKPB3 STKPB2 STKPB1 STKPB0 @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 S7PC10 S7PC9 S7PC8 S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 S6PC10 S6PC9 S6PC8 " " " " " " " " " " " " " " " " " " " " " " " " S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 S1PC10 S1PC9 S1PC8 S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 S0PC10 S0PC9 S0PC8 R/W R/W R/W R/W R/W R/W R R/W W R/W R/W R/W R/W R/W R/W W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W " " " R/W R/W R/W R/W Remarks R Z Y PFLAG ADM mode register ADB data buffer ADR register P1W wakeup register P1M I/O direction P4M I/O direction P5M I/O direction INTRQ INTEN OSCM TC0R PCL PCH P0 data buffer P1 data buffer P4 data buffer P5 data buffer TC0M TC0C STKP stack pointer @YZ index pointer STK7L STK7H STK6L STK6H " " " STK1L STK1H STK0L STK0H Table 5-4. Bit System Register Table of SN8P1702 Note: a). To avoid system error, please be sure to put all the "0" as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. d). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. SONiX TECHNOLOGY CO., LTD Page 51 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1704 System register table Address 082H 083H 084H 086H 0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H 0C0H 0C2H 0C1H 0C4H 0C5H 0C8H 0C9H 0CAH 0CDH 0CEH 0CFH 0D0H 0D1H 0D4H 0D5H 0DAH 0DBH 0DCH 0DDH 0DEH 0DFH 0E7H 0F0H 0F1H 0F2H 0F3H " " " 0FCH 0FDH 0FEH 0FFH Bit7 RBIT7 ZBIT7 YBIT7 DAENB ADENB ADB11 SENB SIOR7 SIOB7 0 0 0 0 0 0 0 0 TC0R7 PC7 TC0ENB TC0C7 TC1ENB TC1C7 TC1R7 GIE @YZ7 S7PC7 S6PC7 " " " S1PC7 S0PC7 Bit6 RBIT6 ZBIT6 YBIT6 DAB6 ADS ADB10 ADCKS START SIOR6 SIOB6 0 0 0 0 0 TC1IRQ TC1IEN WDRST TC0R6 PC6 TC0rate2 TC0C6 TC1rate2 TC1C6 TC1R6 @YZ6 S7PC6 S6PC6 " " " S1PC6 S0PC6 Bit5 Bit4 Bit3 Bit2 RBIT5 RBIT4 RBIT3 RBIT2 ZBIT5 ZBIT4 ZBIT3 ZBIT2 YBIT5 YBIT4 YBIT3 YBIT2 C DAB5 DAB4 DAB3 DAB2 EOC GCHS CHS2 ADB9 ADB8 ADB7 ADB6 ADLEN 0 ADB3 ADB2 SRATE1 SRATE0 0 SCKMD SIOR5 SIOR4 SIOR3 SIOR2 SIOB5 SIOB4 SIOB3 SIOB2 0 P14W P13W P12W 0 0 0 0 0 P14M P13M P12M 0 P44M P43M P42M 0 P54M P53M P52M TC0IRQ 0 SIOIRQ P02IRQ TC0IEN 0 SIOIEN P02IEN WDRate 0 CPUM0 CLKMD TC0R5 TC0R4 TC0R3 TC0R2 PC5 PC4 PC3 PC2 PC11 PC10 P02 P14 P13 P12 P44 P43 P42 P54 P53 P52 TC0rate1 TC0rate0 0 ALOAD0 TC0C5 TC0C4 TC0C3 TC0C2 TC1rate1 TC1rate0 0 ALOAD1 TC1C5 TC1C4 TC1C3 TC1C2 TC1R5 TC1R4 TC1R3 TC1R2 STKPB3 STKPB2 @YZ5 @YZ4 @YZ3 @YZ2 S7PC5 S7PC4 S7PC3 S7PC2 S7PC11 S7PC10 S6PC5 S6PC4 S6PC3 S6PC2 S6PC11 S6PC10 " " " " " " " " " " " " S1PC5 S1PC4 S1PC3 S1PC2 S1PC11 S1PC10 S0PC5 S0PC4 S0PC3 S0PC2 S0PC11 S0PC10 Bit1 Bit0 RBIT1 RBIT0 ZBIT1 ZBIT0 YBIT1 YBIT0 DC Z DAB1 DAB0 CHS1 CHS0 ADB5 ADB4 ADB1 ADB0 SEDGE TXRX SIOR1 SIOR0 SIOB1 SIOB0 P11W P10W 0 0 P11M P10M P41M P40M P51M P50M P01IRQ P00IRQ P01IEN P00IEN STPHX 0 TC0R1 TC0R0 PC1 PC0 PC9 PC8 P01 P00 P11 P10 P41 P40 P51 P50 TC0OUT PWM0OUT TC0C1 TC0C0 TC1OUT PWM1OUT TC1C1 TC1C0 TC1R1 TC1R0 STKPB1 STKPB0 @YZ1 @YZ0 S7PC1 S7PC0 S7PC9 S7PC8 S6PC1 S6PC0 S6PC9 S6PC8 " " " " " " S1PC1 S1PC0 S1PC9 S1PC8 S0PC1 S0PC0 S0PC9 S0PC8 R/W R/W R/W R/W R/W R/W R/W R R/W R/W W R/W W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W " " " R/W R/W R/W R/W Remarks R Z Y PFLAG DAM data register ADM mode register ADB data buffer ADR register SIOM mode register SIOR reload buffer SIOB data buffer P1W wakeup register P2M I/O direction P1M I/O direction P4M I/O direction P5M I/O direction INTRQ INTEN OSCM TC0R PCL PCH P0 data buffer P1 data buffer P4 data buffer P5 data buffer TC0M TC0C TC1M TC1C TC1R STKP stack pointer @YZ index pointer STK7L STK7H STK6L STK6H " " " STK1L STK1H STK0L STK0H Table 5-5. Bit System Register Table of SN8P1704 Note: a). To avoid system error, please be sure to put all the "0" as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. d). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. e). For detail description please refer file of "System Register Quick Reference Table" SONiX TECHNOLOGY CO., LTD Page 52 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1706 System register table Address 080H 081H 082H 083H 084H 085H 086H 087H 0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H 0C0H 0C1H 0C2H 0C4H 0C5H 0C8H 0C9H 0CAH 0CDH 0CEH 0CFH 0D0H 0D1H 0D2H 0D4H 0D5H 0D8H 0D9H 0DAH 0DBH 0DCH 0DDH 0DEH 0DFH 0E6H 0E7H 0F0H 0F1H 0F2H 0F3H " " 0FCH 0FDH 0FEH 0FFH Bit7 LBIT7 HBIT7 RBIT7 ZBIT7 YBIT7 XBIT7 DAENB ADENB ADB11 SENB SIOR7 SIOB7 0 0 0 P47M P57M 0 0 0 TC0R7 PC7 P47 P57 T0ENB T0C7 TC0ENB TC0C7 TC1ENB TC1C7 TC1R7 GIE @HL7 @YZ7 S7PC7 S6PC7 " " S1PC7 S0PC7 Bit6 Bit5 Bit4 LBIT6 LBIT5 LBIT4 HBIT6 HBIT5 HBIT4 RBIT6 RBIT5 RBIT4 ZBIT6 ZBIT5 ZBIT4 YBIT6 YBIT5 YBIT4 XBIT6 XBIT5 XBIT4 DAB6 DAB5 DAB4 ADS EOC GCHS ADB10 ADB9 ADB8 ADCKS ADLEN 0 START SRATE1 SRATE0 SIOR6 SIOR5 SIOR4 SIOB6 SIOB5 SIOB4 0 P15W P14W 0 P15M P14M 0 0 P24M P46M P45M P44M P56M P55M P54M TC1IRQ TC0IRQ T0IRQ TC1IEN TC0IEN T0IEN WDRST Wdrate 0 TC0R6 TC0R5 TC0R4 PC6 PC5 PC4 P15 P14 P24 P46 P45 P44 P56 P55 P54 T0rate2 T0rate1 T0rate0 T0C6 T0C5 T0C4 TC0rate2 TC0rate1 TC0rate0 TC0C6 TC0C5 TC0C4 TC1rate2 TC1rate1 TC1rate0 TC1C6 TC1C5 TC1C4 TC1R6 TC1R5 TC1R4 @HL6 @HL5 @HL4 @YZ6 @YZ5 @YZ4 S7PC6 S7PC5 S7PC4 S6PC6 S6PC5 S6PC4 " " " " " " S1PC6 S1PC5 S1PC4 S0PC6 S0PC5 S0PC4 Bit3 LBIT3 HBIT3 RBIT3 ZBIT3 YBIT3 XBIT3 DAB3 ADB7 ADB3 0 SIOR3 SIOB3 P13W P13M P23M P43M P53M SIOIRQ SIOIEN CPUM0 TC0R3 PC3 PC11 P13 P23 P43 P53 0 T0C3 0 TC0C3 0 TC1C3 TC1R3 STKPB3 @HL3 @YZ3 S7PC3 S7PC11 S6PC3 S6PC11 " " S1PC3 S1PC11 S0PC3 S0PC11 Bit2 LBIT2 HBIT2 RBIT2 ZBIT2 YBIT2 XBIT2 C DAB2 CHS2 ADB6 ADB2 SCKMD SIOR2 SIOB2 P12W P12M P22M P42M P52M P02IRQ P02IEN CLKMD TC0R2 PC2 PC10 P02 P12 P22 P42 P52 0 T0C2 ALOAD0 TC0C2 ALOAD1 TC1C2 TC1R2 STKPB2 @HL2 @YZ2 S7PC2 S7PC10 S6PC2 S6PC10 " " S1PC2 S1PC10 S0PC2 S0PC10 Bit1 Bit0 R/W Remarks LBIT1 LBIT0 R/W L HBIT1 HBIT0 R/W H RBIT1 RBIT0 R/W R ZBIT1 ZBIT0 R/W Z YBIT1 YBIT0 R/W Y XBIT1 XBIT0 R/W X DC Z R/W PFLAG RBNKS0 R/W RBANK DAB1 DAB0 R/W DAM data register CHS1 CHS0 R/W ADM mode register ADB5 ADB4 R ADB data buffer ADB1 ADB0 R/W ADR register SEDGE TXRX R/W SIOM mode register SIOR1 SIOR0 W SIOR reload buffer SIOB1 SIOB0 R/W SIOB data buffer P11W P10W W P1W wakeup register P11M P10M R/W P1M I/O direction P21M P20M R/W P2M I/O direction P41M P40M R/W P4M I/O direction P51M P50M R/W P5M I/O direction P01IRQ P00IRQ R/W INTRQ P01IEN P00IEN R/W INTEN STPHX 0 R/W OSCM TC0R1 TC0R0 W TC0R PC1 PC0 R/W PCL PC9 PC8 R/W PCH P01 P00 R P0 data buffer P11 P10 R/W P1 data buffer P21 P20 R/W P2 data buffer P41 P40 R/W P4 data buffer P51 P50 R/W P5 data buffer 0 0 R/W T0M T0C1 T0C0 R/W T0C TC0OUT PWM0OUT R/W TC0M TC0C1 TC0C0 R/W TC0C TC1OUT PWM1OUT R/W TC1M TC1C1 TC1C0 R/W TC1C TC1R1 TC1R0 W TC1R STKPB1 STKPB0 R/W STKP stack pointer @HL1 @HL0 R/W @HL index pointer @YZ1 @YZ0 R/W @YZ index pointer S7PC1 S7PC0 R/W STK7L S7PC9 S7PC8 R/W STK7H S6PC1 S6PC0 R/W STK6L S6PC9 S6PC8 R/W STK6H " " " " " " " " S1PC1 S1PC0 R/W STK1L S1PC9 S1PC8 R/W STK1H S0PC1 S0PC0 R/W STK0L S0PC9 S0PC8 R/W STK0H Table 5-6. Bit System Register Table of SN8P1706 Note: a). To avoid system error, please be sure to put all the "0" as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. d). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. e). For detail description please refer file of "System Register Quick Reference Table" SONiX TECHNOLOGY CO., LTD Page 53 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SN8P1707/ SN8P1708 System register table Address 080H 081H 082H 083H 084H 085H 086H 087H 0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H 0C0H 0C1H 0C2H 0C4H 0C5H 0C8H 0C9H 0CAH 0CDH 0CEH 0CFH 0D0H 0D1H 0D2H 0D4H 0D5H 0D8H 0D9H 0DAH 0DBH 0DCH 0DDH 0DEH 0DFH 0E6H 0E7H 0F0H 0F1H 0F2H 0F3H " " 0FCH 0FDH 0FEH 0FFH Bit7 LBIT7 HBIT7 RBIT7 ZBIT7 YBIT7 XBIT7 DAENB ADENB ADB11 SENB SIOR7 SIOB7 0 0 P27M P47M P57M 0 0 0 TC0R7 PC7 P27 P47 P57 T0ENB T0C7 TC0ENB TC0C7 TC1ENB TC1C7 TC1R7 GIE @HL7 @YZ7 S7PC7 S6PC7 " " S1PC7 S0PC7 Bit6 Bit5 Bit4 LBIT6 LBIT5 LBIT4 HBIT6 HBIT5 HBIT4 RBIT6 RBIT5 RBIT4 ZBIT6 ZBIT5 ZBIT4 YBIT6 YBIT5 YBIT4 XBIT6 XBIT5 XBIT4 DAB6 DAB5 DAB4 ADS EOC GCHS ADB10 ADB9 ADB8 ADCKS ADLEN 0 START SRATE1 SRATE0 SIOR6 SIOR5 SIOR4 SIOB6 SIOB5 SIOB4 0 P15W P14W 0 P15M P14M P26M P25M P24M P46M P45M P44M P56M P55M P54M TC1IRQ TC0IRQ T0IRQ TC1IEN TC0IEN T0IEN WDRST Wdrate 0 TC0R6 TC0R5 TC0R4 PC6 PC5 PC4 P15 P14 P26 P25 P24 P46 P45 P44 P56 P55 P54 T0rate2 T0rate1 T0rate0 T0C6 T0C5 T0C4 TC0rate2 TC0rate1 TC0rate0 TC0C6 TC0C5 TC0C4 TC1rate2 TC1rate1 TC1rate0 TC1C6 TC1C5 TC1C4 TC1R6 TC1R5 TC1R4 @HL6 @HL5 @HL4 @YZ6 @YZ5 @YZ4 S7PC6 S7PC5 S7PC4 S6PC6 S6PC5 S6PC4 " " " " " " S1PC6 S1PC5 S1PC4 S0PC6 S0PC5 S0PC4 Bit3 LBIT3 HBIT3 RBIT3 ZBIT3 YBIT3 XBIT3 DAB3 ADB7 ADB3 0 SIOR3 SIOB3 P13W P13M P23M P43M P53M SIOIRQ SIOIEN CPUM0 TC0R3 PC3 PC11 P13 P23 P43 P53 0 T0C3 0 TC0C3 0 TC1C3 TC1R3 STKPB3 @HL3 @YZ3 S7PC3 S7PC11 S6PC3 S6PC11 " " S1PC3 S1PC11 S0PC3 S0PC11 Bit2 LBIT2 HBIT2 RBIT2 ZBIT2 YBIT2 XBIT2 C DAB2 CHS2 ADB6 ADB2 SCKMD SIOR2 SIOB2 P12W P12M P22M P42M P52M P02IRQ P02IEN CLKMD TC0R2 PC2 PC10 P02 P12 P22 P42 P52 0 T0C2 ALOAD0 TC0C2 ALOAD1 TC1C2 TC1R2 STKPB2 @HL2 @YZ2 S7PC2 S7PC10 S6PC2 S6PC10 " " S1PC2 S1PC10 S0PC2 S0PC10 Bit1 Bit0 R/W Remarks LBIT1 LBIT0 R/W L HBIT1 HBIT0 R/W H RBIT1 RBIT0 R/W R ZBIT1 ZBIT0 R/W Z YBIT1 YBIT0 R/W Y XBIT1 XBIT0 R/W X DC Z R/W PFLAG RBNKS0 R/W RBANK DAB1 DAB0 R/W DAM data register CHS1 CHS0 R/W ADM mode register ADB5 ADB4 R ADB data buffer ADB1 ADB0 R/W ADR register SEDGE TXRX R/W SIOM mode register SIOR1 SIOR0 W SIOR reload buffer SIOB1 SIOB0 R/W SIOB data buffer P11W P10W W P1W wakeup register P11M P10M R/W P1M I/O direction P21M P20M R/W P2M I/O direction P41M P40M R/W P4M I/O direction P51M P50M R/W P5M I/O direction P01IRQ P00IRQ R/W INTRQ P01IEN P00IEN R/W INTEN STPHX 0 R/W OSCM TC0R1 TC0R0 W TC0R PC1 PC0 R/W PCL PC9 PC8 R/W PCH P01 P00 R P0 data buffer P11 P10 R/W P1 data buffer P21 P20 R/W P2 data buffer P41 P40 R/W P4 data buffer P51 P50 R/W P5 data buffer 0 0 R/W T0M T0C1 T0C0 R/W T0C TC0OUT PWM0OUT R/W TC0M TC0C1 TC0C0 R/W TC0C TC1OUT PWM1OUT R/W TC1M TC1C1 TC1C0 R/W TC1C TC1R1 TC1R0 W TC1R STKPB1 STKPB0 R/W STKP stack pointer @HL1 @HL0 R/W @HL index pointer @YZ1 @YZ0 R/W @YZ index pointer S7PC1 S7PC0 R/W STK7L S7PC9 S7PC8 R/W STK7H S6PC1 S6PC0 R/W STK6L S6PC9 S6PC8 R/W STK6H " " " " " " " " S1PC1 S1PC0 R/W STK1L S1PC9 S1PC8 R/W STK1H S0PC1 S0PC0 R/W STK0L S0PC9 S0PC8 R/W STK0H Table 5-7. Bit System Register Table of SN8P1707/ SN8P1708 Note: a). To avoid system error, please be sure to put all the "0" as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. d). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. e). For detail description please refer file of "System Register Quick Reference Table" SONiX TECHNOLOGY CO., LTD Page 54 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 6 POWER ON RESET OVERVIEW SN8P1700 provides two system resets. One is external reset and the other is low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value. The timing diagram is as following. VDD LVD Detect Level External Reset External Reset Detect Level LVD End of LVD Reset Internal Reset Signal End of External Reset Figure 6-1 Power on Reset Timing Diagram Notice : The working current of the LVD is about 100uA. SONiX TECHNOLOGY CO., LTD Page 55 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC EXTERNAL RESET DESCRIPTION The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system operation. It is necessary that the VDD must be stable. VDD External Reset External Reset Detect Level Internal Reset Signal System Reset End of External Reset Figure 6-2 External Reset Timing Diagram Users must to be sure the VDD stable earlier than external reset (Figure 5-2) or the external reset will fail. The external reset circuit is a simple RC circuit as following. R 20K ohm VDD RST C 0.1uF VSS MCU VCC GND Figure 6-3. External Reset Circuit SONiX TECHNOLOGY CO., LTD Page 56 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC In worse-power condition as brown out reset. The reset pin may keep high level but the VDD is low voltage. That makes the system reset fail and chip error. To connect a diode from reset pin to VDD is a good solution. The circuit can force the capacitor to release electric charge and drop the voltage, and solve the error. DIODE R 20K ohm VDD RST C 0.1uF VSS MCU VCC GND Figure 6-4. External Reset Circuit with Diode LOW VOLTAGE DETECTOR (LVD) DESCRIPTION The LVD is a low voltage detector. It detects VDD level and reset the system as the VDD lower than the desired voltage. The detect level is 2.4V. If the VDD lower than 2.4V, the system resets. The LVD function is controlled by code option. Users can turn on it for special application like worse power condition. LVD work with external reset function. They are OR active. VDD LVD Detect Level LVD System Reset End of LVD Reset Figure 6-5. LVD Timing Diagram The LVD can protect system to work well under brownout reset. But it is a high consumptive circuit. In 3V condition, the LVD consumes about 100uA. It is a very large consumption for battery system. So the LVD supports AC system well. Notice: LVD is selected by code option. SONiX TECHNOLOGY CO., LTD Page 57 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 7 OSCILLATORS OVERVIEW The SN8P1700 highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed clock frequency is supplied through on-chip RC oscillator circuit. The external high-speed clock and the internal low-speed clock can be system clock (Fosc). And the system clock is divided by 4 to be the instruction cycle (Fcpu). Fcpu = Fosc / 4 The system clock is required by the following peripheral modules: Basic timer (T0) Timer counter 0 (TC0) Timer counter 1 (TC1) Watchdog timer Serial I/O interface (SIO) AD converter PWM output (PWM0, PWM1) Buzzer output (TC0OUT, TC1OUT) CLOCK BLOCK DIAGRAM HXRC(1:0) is code option *00= RC *01 =32 Khz Oscillator *10 = High Speed Oscillator (>10Mhz) *11 = Standard Oscillator (4Mhz) STPHX XIN XOUT CPUM0 LXOSC. CPUM0 fl HXRC OSG Divided by 2 1 : Disable 0 : Enable CLKMD fosc/4 CPUM0 HXOSC. fh Divided by 2 Divided by 4 fcpu OSG : Oscillator Safe Guard 1 : Disable -- System Default 0 : Enable Figure 7-1. Clock Block Diagram HXOSC: External high-speed clock. LXOSC: Internal low-speed clock. OSG: Oscillator safe guard. SONiX TECHNOLOGY CO., LTD Page 58 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC OSCM REGISTER DESCRIPTION The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock source and rate. OSCM initial value = 000x 000x 0CAH OSCM Bit 7 0 Bit 6 WDRST R/W Bit 5 Wdrate R/W Bit 4 0 Bit 3 CPUM0 R/W Bit 2 CLKMD R/W Bit 1 STPHX R/W Bit 0 0 - STPHX: Eternal high-speed oscillator control bit. 0 = free run, 1 = stop. This bit just only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC oscillator is still running. CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. CPUM0: CPU operating mode control bit. 0 = normal, 1 = sleep (power down) mode to turn off both high/low clock. Notice: The bit 7 of OSCM register must be "0", or the system will be error. SONiX TECHNOLOGY CO., LTD Page 59 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC EXTERNAL HIGH-SPEED OSCILLATOR SN8P1700 can be operated in four different oscillator modes. There are external RC oscillator modes, high crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode (32K code option). For different application, the users can select one of satiable oscillator mode by programming code option to generate system high-speed clock source after reset. Example: Stop external high-speed oscillator. B0BSET FSTPHX ; To stop external high-speed oscillator only. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). OSCILLATOR MODE CODE OPTION SN8P1700 has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main purpose is to support different oscillator types and frequencies. High-speed crystal needs more current but the low one doesn't. For crystals, there are three steps to select. If the oscillator is RC type, to select "RC" and the system will divide the frequency by 2 automatically. User can select oscillator mode from Code Option table before compiling. The table is as follow. Code Option 00 01 10 11 Oscillator Mode RC mode 32K 12M 4M Remark Output the Fcpu square wave from Xout pin. 32768Hz 12MHz ~ 16MHz 3.58MHz OSCILLATOR DEVIDE BY 2 CODE OPTION SN8P1700 has an external clock divide by 2 function. It is a code option called "High_Clk / 2". If "High_Clk / 2" is enabled, the external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If "High_Clk / 2" is disabled, the external clock frequency is divided by 4 for the Fcpu. The Fcpu is equal to Fosc/4. Note: In RC mode, "High_Clk / 2" is always enabled. OSCILLATOR SAFE GUARD CODE OPTION SN8P1700 builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and stops high frequency noise into system from external oscillator circuit. This function makes system to work better under AC noisy conditions. SONiX TECHNOLOGY CO., LTD Page 60 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SYSTEM OSCILLATOR CIRCUITS 20PF VDD XIN CRYSTAL 20PF XOUT VSS MCU Figure 7-2. Crystal/Ceramic Oscillator R VDD XIN C XOUT VSS MCU Figure 7-3. RC Oscillator External Clock Input VDD XIN XOUT VSS MCU Figure 7-4. External clock input Note1: The VDD and VSS of external oscillator circuit must be from the micro-controller. Don't connect them from the neighbor power terminal. Note2: The external clock input mode can select RC type oscillator or crystal type oscillator of the code option and input the external clock into XIN pin. Note3: In RC type oscillator code option situation, the external clock's frequency is divided by 2. Note4: The power and ground of external oscillator circuit must be connected from the micro-controller's VDD and VSS. It is necessary to step up the performance of the whole system. SONiX TECHNOLOGY CO., LTD Page 61 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC External RC Oscillator Frequency Measurement There are two ways to get the Fosc frequency of external RC oscillator. One measures the XOUT output waveform. Under external RC oscillator mode, the XOUT outputs the square waveform whose frequency is Fcpu. The other measures the external RC frequency by instruction cycle (Fcpu). The external RC frequency is the Fcpu multiplied by 4. We can get the Fosc frequency of external RC from the Fcpu frequency. The sub-routine to get Fcpu frequency of external oscillator is as the following. Example: Fcpu instruction cycle of external oscillator B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. @@: B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. SONiX TECHNOLOGY CO., LTD Page 62 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC INTERNAL LOW-SPEED OSCILLATOR The internal low-speed oscillator is built in the micro-controller. The low-speed clock's source is a RC type oscillator circuit. The low-speed clock can supplies clock for system clock, timer counter, watchdog timer, SIO clock source and so on. Example: Stop internal low-speed oscillator. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can't be turned off individually. It is controlled by CPUM0 bit of OSCM register. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relative between the RC frequency and voltage is as following. Internal RC vs. VDD 40 35 35.343 32.008 38.678 Fintrc (KHz) 30 25 22.003 25.338 28.673 20 15 11.998 15.333 18.668 10 7.329 8.663 5 0 1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 VDD (Volts) Figure 7-5. Internal RC vs. VDD Diagram Example: To measure the internal RC frequency is by instruction cycle (Fcpu). The internal RC frequency is the Fcpu multiplied by 4. So we can get the Fosc frequency of internal RC from the Fcpu frequency. B0BSET B0BSET @@: B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. P1M.0 FCLKMD ; Set P1.0 to be output mode for outputting Fcpu toggle signal. ; Switch the system clock to internal low-speed clock mode. SONiX TECHNOLOGY CO., LTD Page 63 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SYSTEM MODE DESCRIPTION OVERVIEW The chip is featured with low power consumption by switching around three different modes as following. High-speed mode Low-speed mode Power-down mode (Sleep mode) In actual application, the user can adjust the chip's controller to work in these three modes by using OSCM register. At the high-speed mode, the instruction cycle (Fcpu) is Fosc/4. At the low-speed mode and 3V, the Fcpu is 16KHz/4. NORMAL MODE In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is 3.58MHz/4 = 895KHz. All software and hardware are executed and working. In normal mode, system can get into power down mode and slow mode. SLOW MODE In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD = 1, the system switch to slow mode. In slow mode, the system works as normal mode but the slower clock. The system in slow mode can get into normal mode and power down mode. To set STPHX = 1 to stop the external high-speed oscillator, and then the system consumes less power. POWER DOWN MODE The power down mode is also called sleep mode. The chip stops working as sleeping status. The power consumption is very less almost to zero. The power down mode is usually applied to low power consuming system as battery power productions. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal. SONiX TECHNOLOGY CO., LTD Page 64 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SYSTEM MODE CONTROL SN8P1700 SYSTEM MODE BLOCK DIAGRAM Power Down Mode (Sleep Mode) P0, P1 wake-up function active. External reset circuit active. CPUM0 = 01 CLKMD = 1 Normal Mode CLKMD = 0 Slow Mode Figure 7-6. SN8P1700 System Mode Block Diagram Operating mode description POWER DOWN NORMAL SLOW (SLEEP) Running By STPHX Stop Running Running Stop Executing Executing Stop *Active *Active Inactive *Active *Active Inactive *Active *Active Inactive Active Active Inactive All active All active All inactive All active All active All inactive P0, P1, Reset Table 7-1. Operating Mode Description MODE HX osc. LX osc. CPU instruction T0 timer TC0 timer TC1 timer Watchdog timer Internal interrupt External interrupt Wakeup source REMARK * Active by programm. SONiX TECHNOLOGY CO., LTD Page 65 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SYSTEM MODE SWITCHING Switch normal/slow mode to power down (sleep) mode. CPUM0 = 1 B0BSET FCPUM0 ; set the system into power down mode. During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. Switch normal mode to slow mode. B0BSET B0BSET FCLKMD FSTPHX ;To set CLKMD = 1, Change the system into slow mode ;To stop external high-speed oscillator for power saving. Switch slow mode to normal mode If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable. B0BCLR B0MOV DECMS JMP B0BCLR FSTPHX Z, #27 Z @B FCLKMD ; Turn on the external high-speed oscillator. ; If VDD = 5V, internal RC=32KHz (typical) will delay ; 0.125ms X 81 = 10.125ms for external clock stable ; ; Change the system back to the normal mode @@: SONiX TECHNOLOGY CO., LTD Page 66 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC WAKEUP TIME OVERVIEW The external high-speed oscillator needs a delay time from stopping to operating. The delay is very necessary and makes the oscillator to work stably. Some conditions during system operating, the external high-speed oscillator often runs and stops. Under these condition, the delay time for external high-speed oscillator restart is called wakeup time. There are two conditions need wakeup time. One is power down mode to normal mode. The other one is slow mode to normal mode. For the first case, SN8P1700 provides 2048 oscillator clocks to be the wakeup time. But in the last case, users need to make the wakeup time by themselves. HARDWARE WAKEUP When the system is in power down mode (sleep mode), the external high-speed oscillator stops. For wakeup into normal, SN8P1700 provides 2048 external high-speed oscillator clocks to be the wakeup time for warming up the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as following. The wakeup time = 1/Fosc * 2048 (sec) Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the wakeup time, the system goes into normal mode. The wakeup time of P0, P1 wakeup function is as following. The wakeup time = 1/Fosc * 2048 = 0.57 ms The wakeup time = 1/Fosc * 2048 = 62.5 ms (Fosc = 3.58MHz) (Fosc=32768Hz) Under power down mode (sleep mode), there are only I/O ports with wakeup function making the system to return normal mode. The Port 0 and Port 1 have wakeup function. Port 0's wakeup function always enables. The Port 1 controls by the P1W register. P1W initial value = xx00 0000 0C0H P1W Bit 7 0 Bit 6 0 Bit 5 P15W W Bit 4 P14W W Bit 3 P13W W Bit 2 P12W W Bit 1 P11W W Bit 0 P10W W P10W~P15W: Port 1 wakeup function control bits. 0 = none wakeup function, 1 = Enable each pin of Port 1 wakeup function. Note: For SN8P1702 the P1W register only obtains P10W and P11W. For SN8P1704 the P1W register only obtain P10W~P14W. SONiX TECHNOLOGY CO., LTD Page 67 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 8 TIMERS COUNTERS WATCHDOG TIMER (WDT) The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program get into the unknown status by noise interference, WDT's overflow signal will reset this chip and restart operation. The instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program within a given period. If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate different output timings, the user can control watchdog timer by modifying Wdrate control bits of OSCM register. The watchdog timer will be disabled at green and power down modes. OSCM initial value = 0000 000x 0CAH OSCM Bit 7 0 Bit 6 WDRST R/W Bit 5 Wdrate R/W Bit 4 Bit 3 CPUM0 R/W Bit 2 CLKMD R/W Bit 1 STPHX R/W Bit 0 - Notice: The bit 7 must be "0", or the system will be error. Wdrate: Watchdog timer rate select bit. 0 =14th, 1 = 8th. WDRST : Watch dog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer's counter. Wdrate 0 1 Watchdog timer overflow time External high-speed oscillator 1 / ( fcpu / 214 / 16 ) = 293 ms, Fosc=3.58MHz 1 / ( fcpu / 214 / 16 ) = 32 s, Fosc=32768Hz 1 / ( fcpu / 28 / 16 ) = 4.5 ms, Fosc=3.58MHz 1 / ( fcpu / 28 / 16 ) = 500 ms, Fosc=32768Hz Figure 8-1. Watchdog timer overflow time table Note: The watch dog timer can be enabled or disabled by the code option. Example: An operation of watch-dog timer is as following. To clear the watchdog timer's counter in the top of the main routine of the program. Main: B0BSET . CALL CALL . . . JMP FWDRST . SUB1 SUB2 . . . MAIN ; Clear the watchdog timer's counter. SONiX TECHNOLOGY CO., LTD Page 68 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC BASIC TIMER 0 (T0) OVERVIEW The basic timer (T0) is an 8-bit binary up counter. It uses T0M register to select T0C's input clock for counting a precision time. If the T0 timer has occur an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger T0 interrupt to request interrupt service. The main purposes of the T0 basic timer is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. T0enb Internal data bus pre_load fcpu / 2(8-T0Rate) T0C 8-bit binary counter T0 Time out Figure 8-2. Basic Timer T0 Block Diagram T0M REGISTER DESCRIPTION The T0M is the basic timer mode register which is a 8-bit read/write register and only used the high nibble. By loading different value into the T0M register, users can modify the basic timer clock dynamically as program executing. Eight rates for T0 timer can be selected by T0RATE0 ~ T0RATE2 bits. The range is from fcpu/2 to fcpu/256. The T0M initial value is zero and the rate is fcpu/256. The bit7 of T0M called T0ENB is the control bit to start T0 timer. The combination of these bits is to determine the T0 timer clock frequency and the intervals. T0M initial value = 0000 xxxx 0D8H T0M Bit 7 T0ENB R/W Bit 6 T0RATE2 R/W Bit 5 T0RATE1 R/W Bit 4 T0RATE0 R/W Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 - T0ENB: T0 timer control bit. 0 = disable, 1 = enable. T0RATE2~T0RATE0: The T0 timer's clock source select bits. 000 = fcpu/256, 001 = fcpu/128, ... , 110 = fcpu/4, 111 = fcpu/2. SONiX TECHNOLOGY CO., LTD Page 69 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC T0C COUNTING REGISTER T0C is an 8-bit counter register for the basic timer (T0). T0C must be reset whenever the T0ENB is set "1" to start the basic timer. T0C is incremented by one with every clock pulse which frequency is determined by T0RATE0 ~ T0RATE2. When T0C has incremented to "0FFH", it will be cleared to "00H" in next clock and an overflow generated. Under T0 interrupt service request (T0IEN) enable condition, the T0 interrupt request flag will be set "1" and the system executes the interrupt service routine. The T0C has no auto reload function. After T0C overflow, the T0C is continuing counting. Users need to reset T0C value to get a accurate time. T0C initial value = xxxx xxxx 0D9H T0C Bit 7 T0C7 R/W Bit 6 T0C6 R/W Bit 5 T0C5 R/W Bit 4 T0C4 R/W Bit 3 T0C3 R/W Bit 2 T0C2 R/W Bit 1 T0C1 R/W Bit 0 T0C0 R/W T0RATE 000 001 010 011 100 101 110 111 T0CLOCK fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2 High speed mode (fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us Low speed mode (fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms Figure 8-3. The Timing Table of Basic Timer T0. The equation of T0C initial value is as following. T0C initial value = 256 - (T0 interrupt interval time * input clock) Example : To set 10ms interval time for T0 interrupt at 3.58MHz high-speed mode. T0C value (74H) = 256 (10ms * fcpu/64) T0C initial value = 256 - (T0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H SONiX TECHNOLOGY CO., LTD Page 70 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC T0 BASIC TIMER OPERATION SEQUENCE The T0 basic timer's sequence of operation can be following. Set the T0C initial value to setup the interval time. Set the T0ENB to be "1" to enable T0 basic timer. T0C is incremented by one with each clock pulse which frequency is corresponding to T0M selection. T0C overflow when T0C from FFH to 00H. When T0C overflow occur, the T0IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the T0C value and resume the T0 timer operation. Example: Setup the T0M and T0C. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET FT0IEN FT0ENB A,#20H T0M,A A,#74H T0C,A FT0IEN FT0IRQ FT0ENB ; To disable T0 interrupt service ; To disable T0 timer ; ; To set T0 clock = fcpu / 64 ; To set T0C initial value = 74H (To set T0 interval = 10 ms) ; To enable T0 interrupt service ; To clear T0 interrupt request ; To enable T0 timer Example: T0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: POP B0XCH RETI A, ACCBUF ; Pop ;Restore ACC value ; Exit interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check T0IRQ ; T0IRQ = 0, exit interrupt vector ; Reset T0IRQ ; Reload T0C ; T0 interrupt service routine ; End of T0 interrupt service routine and exit interrupt vector 8 INT_SERVICE ; Interrupt vector FT0IRQ EXIT_INT FT0IRQ A,#74H T0C,A . . EXIT_INT . . SONiX TECHNOLOGY CO., LTD Page 71 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TIMER COUNTER 0 (TC0) OVERVIEW The timer counter 0 (TC0) is used to generate an interrupt request when a specified time interval has elapsed. TC0 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC0R) into which you write the Aload0 TC0R reload data buffer Internal P5.4 I/O circuit Buzzer TC0out Auto. reload O 2 P5.4 R Compare PWM PWM0OUT TC0enb load S fcpu / 2(8-TC0Rate) CPUM0 TC0C 8-bit binary counter TC0 Time out counter reference value, and an 8-bit counter register (TC0C) whose value is automatically incremented by counter logic. Figure 8-4. Timer Count TC0 Block Diagram The main purposes of the TC0 timer counter is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ0 pin (P5.4). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM0OUT pin (P5.4). SONiX TECHNOLOGY CO., LTD Page 72 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0M MODE REGISTER The TC0M is the timer counter mode register, which is an 8-bit read/write register. By loading different value into the TC0M register, users can modify the timer counter clock frequency dynamically when program executing. Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC0M initial value is zero and the rate is fcpu/256. The bit7 of TC0M called TC0ENB is the control bit to start TC0 timer. The combination of these bits is to determine the TC0 timer clock frequency and the intervals. TC0M initial value = 0000 0000 0DAH TC0M Bit 7 TC0ENB R/W Bit 6 Bit 5 Bit 4 TC0RATE2 TC0RATE1 TC0RATE0 R/W R/W R/W Bit 3 0 - Bit 2 ALOAD0 R/W Bit 1 TC0OUT R/W Bit 0 PWM0OUT R/W TC0ENB: TC0 counter/BZ0/PWM0OUT enable bit. 0 = disable, 1 = enable. TC0RATE2~TC0RATE0: TC0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, ... , 110 = fcpu/4, 111 = fcpu/2. ALOAD0: TC0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC0OUT: TC0 time-out toggle signal output control bit. 0 = To disable TC0 signal output and to enable P5.4's I/O function, 1 = To enable TC0's signal output and to disable P5.4's I/O function. (Auto-disable the PWM0OUT function.) PWM0OUT: TC0's PWM output control bit. 0 = To disable the PWM output, 1 = To enable the PWM output (The TC0OUT control bit must = 0 ) Note: Bit3 must set to 0.. Note: The ICE S8KC do not support the PWM0OUT and TC0OUT Function. The PWM0OUT and TC0OUT must use the S8KD ICE (or later) to verify the function. SONiX TECHNOLOGY CO., LTD Page 73 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0C COUNTING REGISTER TC0C is an 8-bit counter register for the timer counter (TC0). TC0C must be reset whenever the TC0ENB is set "1" to start the timer counter. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to "0FFH", it is will be cleared to "00H" in next clock and an overflow is generated. Under TC0 interrupt service request (TC0IEN) enable condition, the TC0 interrupt request flag will be set "1" and the system executes the interrupt service routine. TC0C initial value = xxxx xxxx 0DBH TC0C Bit 7 TC0C7 R/W Bit 6 TC0C6 R/W Bit 5 TC0C5 R/W Bit 4 TC0C4 R/W Bit 3 TC0C3 R/W Bit 2 TC0C2 R/W Bit 1 TC0C1 R/W Bit 0 TC0C0 R/W TC0RATE TC0CLOCK 000 001 010 011 100 101 110 111 fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2 High speed mode (fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us Low speed mode (fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms Table 8-1. The Timing Table of Timer Count TC0 The equation of TC0C initial value is as following. TC0C initial value = 256 - (TC0 interrupt interval time * input clock) Example: To set 10ms interval time for TC0 interrupt at 3.58MHz high-speed mode. TC0C value (74H) = 256 (10ms * fcpu/64) TC0C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H SONiX TECHNOLOGY CO., LTD Page 74 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0R AUTO-LOAD REGISTER TC0R is an 8-bit register for the TC0 auto-reload function. TC0R's value applies to TC0OUT and PWM0OUT functions.. Under TC0OUT application, users must enable and set the TC0R register. The main purpose of TC0R is as following. Store the auto-reload value and set into TC0C when the TC0C overflow. (ALOAD0 = 1). Store the duty value of PWM0OUT function. TC0R initial value = xxxx xxxx 0CDH TC0R Bit 7 TC0R7 W Bit 6 TC0R6 W Bit 5 TC0R5 W Bit 4 TC0R4 W Bit 3 TC0R3 W Bit 2 TC0R2 W Bit 1 TC0R1 W Bit 0 TC0R0 W The equation of TC0R initial value is like TC0C as following. TC0R initial value = 256 - (TC0 interrupt interval time * input clock) Note: The TC0R is write-only register can't be process by INCMS, DECMS instructions. SONiX TECHNOLOGY CO., LTD Page 75 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0 TIMER COUNTER OPERATION SEQUENCE The TC0 timer counter's sequence of operation can be following. Set the TC0C initial value to setup the interval time. Set the TC0ENB to be "1" to enable TC0 timer counter. TC0C is incremented by one with each clock pulse which frequency is corresponding to T0M selection. TC0C overflow when TC0C from FFH to 00H. When TC0C overflow occur, the TC0IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the TC0C value and resume the TC0 timer operation. Example: Setup the TC0M and TC0C without auto-reload function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A FTC0IEN FTC0IRQ FTC0ENB ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = fcpu / 64 ; To set TC0C initial value = 74H ;(To set TC0 interval = 10 ms) ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer Example: Setup the TC0M and TC0C with auto-reload function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A TC0R,A FTC0IEN FTC0IRQ FTC0ENB ALOAD0 ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = fcpu / 64 ; To set TC0C initial value = 74H ; (To set TC0 interval = 10 ms) ; To set TC0R auto-reload register ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer ; To enable TC0 auto-reload function. SONiX TECHNOLOGY CO., LTD Page 76 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: TC0 interrupt service routine without auto-reload function. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; Reload TC0C ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector FTC0IRQ EXIT_INT FTC0IRQ A,#74H TC0C,A . . EXIT_INT . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector Example: TC0 interrupt service routine with auto-reload. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . JMP . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector FTC0IRQ EXIT_INT FTC0IRQ . . EXIT_INT . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 77 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0 CLOCK FREQUENCY OUTPUT (BUZZER) TC0 timer counter provides a frequency output function. By setting the TC0 clock frequency, the clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0 output signal divides by 2. The TC0 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency. Figure 8-5. The TC0OUT Pulse Frequency Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The TC0OUT frequency is 1KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 2KHz. The TC0 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 131. MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET A,#01100000B TC0M,A A,#131 TC0C,A TC0R,A FTC0OUT FALOAD0 FTC0ENB ; Set the TC0 rate to Fcpu/4 ; Set the auto-reload reference value ; Enable TC0 output to P5.4 and disable P5.4 I/O function ; Enable TC0 auto-reload function ; Enable TC0 timer SONiX TECHNOLOGY CO., LTD Page 78 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0OUT FREQUENCY TABLE Fosc = 4MHz, TC0 Rate = Fcpu/8 TC0R TC0OUT (KHz) 0.2441 0.2451 0.2461 0.2470 0.2480 0.2490 0.2500 0.2510 0.2520 0.2530 0.2541 0.2551 0.2561 0.2572 0.2583 0.2593 0.2604 0.2615 0.2626 0.2637 0.2648 0.2660 0.2671 0.2682 0.2694 0.2706 0.2717 0.2729 0.2741 0.2753 0.2765 0.2778 0.2790 0.2803 0.2815 0.2828 0.2841 0.2854 0.2867 0.2880 0.2894 0.2907 0.2921 0.2934 0.2948 0.2962 0.2976 0.2990 0.3005 0.3019 0.3034 0.3049 0.3064 0.3079 0.3094 0.3109 TC0R TC0OUT (KHz) 0.3125 0.3141 0.3157 0.3173 0.3189 0.3205 0.3222 0.3238 0.3255 0.3272 0.3289 0.3307 0.3324 0.3342 0.3360 0.3378 0.3397 0.3415 0.3434 0.3453 0.3472 0.3492 0.3511 0.3531 0.3551 0.3571 0.3592 0.3613 0.3634 0.3655 0.3676 0.3698 0.3720 0.3743 0.3765 0.3788 0.3811 0.3834 0.3858 0.3882 0.3906 0.3931 0.3956 0.3981 0.4006 0.4032 0.4058 0.4085 0.4112 0.4139 0.4167 0.4195 0.4223 0.4252 0.4281 0.4310 TC0R TC0OUT (KHz) 0.4340 0.4371 0.4401 0.4433 0.4464 0.4496 0.4529 0.4562 0.4596 0.4630 0.4664 0.4699 0.4735 0.4771 0.4808 0.4845 0.4883 0.4921 0.4960 0.5000 0.5040 0.5081 0.5123 0.5165 0.5208 0.5252 0.5297 0.5342 0.5388 0.5435 0.5482 0.5531 0.5580 0.5631 0.5682 0.5734 0.5787 0.5841 0.5896 0.5952 0.6010 0.6068 0.6127 0.6188 0.6250 0.6313 0.6378 0.6443 0.6510 0.6579 0.6649 0.6720 0.6793 0.6868 0.6944 0.7022 TC0R TC0OUT (KHz) 0.7102 0.7184 0.7267 0.7353 0.7440 0.7530 0.7622 0.7716 0.7813 0.7911 0.8013 0.8117 0.8224 0.8333 0.8446 0.8562 0.8681 0.8803 0.8929 0.9058 0.9191 0.9328 0.9470 0.9615 0.9766 0.9921 1.0081 1.0246 1.0417 1.0593 1.0776 1.0965 1.1161 1.1364 1.1574 1.1792 1.2019 1.2255 1.2500 1.2755 1.3021 1.3298 1.3587 1.3889 1.4205 1.4535 1.4881 1.5244 1.5625 1.6026 1.6447 1.6892 1.7361 1.7857 1.8382 1.8939 TC0R TC0OUT (KHz) 1.9531 2.0161 2.0833 2.1552 2.2321 2.3148 2.4038 2.5000 2.6042 2.7174 2.8409 2.9762 3.1250 3.2895 3.4722 3.6765 3.9063 4.1667 4.4643 4.8077 5.2083 5.6818 6.2500 6.9444 7.8125 8.9286 10.4167 12.5000 15.6250 20.8333 31.2500 62.5000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Table 8-2. TC0OUT Frequency Table for Fosc = 4MHz, TC0 Rate = Fcpu/8 SONiX TECHNOLOGY CO., LTD Page 79 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Fosc = 16MHz, TC0 Rate = Fcpu/8 TC0R TC0OUT (KHz) 0.9766 0.9804 0.9843 0.9881 0.9921 0.9960 1.0000 1.0040 1.0081 1.0121 1.0163 1.0204 1.0246 1.0288 1.0331 1.0373 1.0417 1.0460 1.0504 1.0549 1.0593 1.0638 1.0684 1.0730 1.0776 1.0823 1.0870 1.0917 1.0965 1.1013 1.1062 1.1111 1.1161 1.1211 1.1261 1.1312 1.1364 1.1416 1.1468 1.1521 1.1574 1.1628 1.1682 1.1737 1.1792 1.1848 1.1905 1.1962 1.2019 1.2077 1.2136 1.2195 1.2255 1.2315 1.2376 1.2438 TC0R TC0OUT (KHz) 1.2500 1.2563 1.2626 1.2690 1.2755 1.2821 1.2887 1.2953 1.3021 1.3089 1.3158 1.3228 1.3298 1.3369 1.3441 1.3514 1.3587 1.3661 1.3736 1.3812 1.3889 1.3966 1.4045 1.4124 1.4205 1.4286 1.4368 1.4451 1.4535 1.4620 1.4706 1.4793 1.4881 1.4970 1.5060 1.5152 1.5244 1.5337 1.5432 1.5528 1.5625 1.5723 1.5823 1.5924 1.6026 1.6129 1.6234 1.6340 1.6447 1.6556 1.6667 1.6779 1.6892 1.7007 1.7123 1.7241 TC0R TC0OUT (KHz) 1.7361 1.7483 1.7606 1.7730 1.7857 1.7986 1.8116 1.8248 1.8382 1.8519 1.8657 1.8797 1.8939 1.9084 1.9231 1.9380 1.9531 1.9685 1.9841 2.0000 2.0161 2.0325 2.0492 2.0661 2.0833 2.1008 2.1186 2.1368 2.1552 2.1739 2.1930 2.2124 2.2321 2.2523 2.2727 2.2936 2.3148 2.3364 2.3585 2.3810 2.4038 2.4272 2.4510 2.4752 2.5000 2.5253 2.5510 2.5773 2.6042 2.6316 2.6596 2.6882 2.7174 2.7473 2.7778 2.8090 TC0R TC0OUT (KHz) 2.8409 2.8736 2.9070 2.9412 2.9762 3.0120 3.0488 3.0864 3.1250 3.1646 3.2051 3.2468 3.2895 3.3333 3.3784 3.4247 3.4722 3.5211 3.5714 3.6232 3.6765 3.7313 3.7879 3.8462 3.9063 3.9683 4.0323 4.0984 4.1667 4.2373 4.3103 4.3860 4.4643 4.5455 4.6296 4.7170 4.8077 4.9020 5.0000 5.1020 5.2083 5.3191 5.4348 5.5556 5.6818 5.8140 5.9524 6.0976 6.2500 6.4103 6.5789 6.7568 6.9444 7.1429 7.3529 7.5758 TC0R TC0OUT (KHz) 7.8125 8.0645 8.3333 8.6207 8.9286 9.2593 9.6154 10.0000 10.4167 10.8696 11.3636 11.9048 12.5000 13.1579 13.8889 14.7059 15.6250 16.6667 17.8571 19.2308 20.8333 22.7273 25.0000 27.7778 31.2500 35.7143 41.6667 50.0000 62.5000 83.3333 125.0000 250.0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Table 8-3. TC0OUT Frequency Table for Fosc = 16MHz, TC0 Rate = Fcpu/8 SONiX TECHNOLOGY CO., LTD Page 80 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TIMER COUNTER 1 (TC1) OVERVIEW The timer counter 1 (TC1) is used to generate an interrupt request when a specified time interval has elapsed. TC1 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC1R) into which you write the Aload1 TC1R reload data buffer Internal P5.3 I/O circuit Buzzer TC1out Auto. reload O 2 P5.3 R Compare PWM PWM1OUT TC1enb load S fcpu /2(8-TC1Rate) CPUM0 TC1C 8-bit binary counter TC1 Time out counter reference value, and an 8-bit counter register (TC1C) whose value is automatically incremented by counter logic. Figure 8-6. Timer Count TC1 Block Diagram The main purposes of the TC1 timer is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1OUT pin (P5.3). SONiX TECHNOLOGY CO., LTD Page 81 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC1M MODE REGISTER The TC1M is an 8-bit read/write timer mode register. By loading different value into the TC1M register, users can modify the timer clock frequency dynamically as program executing. Eight rates for TC1 timer can be selected by TC1RATE0 ~ TC1RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC1M initial value is zero and the rate is fcpu/256. The bit7 of TC1M called TC1ENB is the control bit to start TC1 timer. The combination of these bits is to determine the TC1 timer clock frequency and the intervals. TC1M initial value = 0000 0000 0DCH TC1M Bit 7 TC1ENB R/W Bit 6 Bit 5 Bit 4 TC1RATE2 TC1RATE1 TC1RATE0 R/W R/W R/W Bit 3 0 - Bit 2 ALOAD1 R/W Bit 1 TC1OUT R/W Bit 0 PWM1OUT R/W TC1ENB: TC1 counter/BZ1/PWM1OUT enable bit. 0 = disable, 1 = enable. TC1RATE2~TC1RATE0: TC1 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, ... , 110 = fcpu/4, 111 = fcpu/2. ALOAD1: TC1 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC1OUT: TC1 time-out toggle signal output control bit. 0 = To disable TC1 signal output and to enable P5.3's I/O function, 1 = To enable TC1's signal output and to disable P5.3's I/O function. (Auto-disable the PWM1OUT function.) PWM1OUT: TC1's PWM output control bit. 0 = To disable the PWM output, 1 = To enable the PWM output (The TC1OUT control bit must = 0 ) Note: Bit3 must set to 0.. Note: The S8KC ICE do not support the PWM1OUT and TC1OUT Function. The PWM1OUT and TC1OUT must use the S8KD ICE (or later) to verify the function. SONiX TECHNOLOGY CO., LTD Page 82 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC1C COUNTING REGISTER TC1C is an 8-bit counter register for the timer counter (TC1). TC1C must be reset whenever the TC1ENB is set "1" to start the timer. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to "0FFH", it is will be cleared to "00H" in next clock and an overflow is generated. Under TC1 interrupt service request (TC1IEN) enable condition, the TC1 interrupt request flag will be set "1" and the system executes the interrupt service routine. TC1C initial value = xxxx xxxx 0DDH TC1C Bit 7 TC1C7 R/W Bit 6 TC1C6 R/W Bit 5 TC1C5 R/W Bit 4 TC1C4 R/W Bit 3 TC1C3 R/W Bit 2 TC1C2 R/W Bit 1 TC1C1 R/W Bit 0 TC1C0 R/W The interval time of TC1 basic timer table. TC1RATE 000 001 010 011 100 101 110 111 TC1CLOC K fcpu/256 fcpu/128 fcpu/64 fcpu/32 fcpu/16 fcpu/8 fcpu/4 fcpu/2 High speed mode (fcpu = 3.58MHz / 4) Max overflow interval One step = max/256 73.2 ms 286us 36.6 ms 143us 18.3 ms 71.5us 9.15 ms 35.8us 4.57 ms 17.9us 2.28 ms 8.94us 1.14 ms 4.47us 0.57 ms 2.23us Low speed mode (fcpu = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms Table 8-4. The Timing Table of Timer Count TC1 The equation of TC1C initial value is as following. TC1C initial value = 256 - (TC1 interrupt interval time * input clock) Example: To set 10ms interval time for TC1 interrupt at 3.58MHz high-speed mode. TC1C value (74H) = 256 (10ms * fcpu/64) TC1C initial value = 256 - (TC1 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (10-2 * 3.58 * 106 / 4 / 64) = 116 = 74H SONiX TECHNOLOGY CO., LTD Page 83 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC1R AUTO-LOAD REGISTER TC1R is an 8-bit register for the TC1 auto-reload function. TC1R's value applies to TC1OUT and PWM1OUT functions. Under TC1OUT application, users must enable and set the TC1R register. The main purpose of TC1R is as following. Store the auto-reload value and set into TC1C when the TC1C overflow. (ALOAD1 = 1). Store the duty value of PWM1OUT function. TC1R initial value = xxxx xxxx 0DEH TC1R Bit 7 TC1R7 W Bit 6 TC1R6 W Bit 5 TC1R5 W Bit 4 TC1R4 W Bit 3 TC1R3 W Bit 2 TC1R2 W Bit 1 TC1R1 W Bit 0 TC1R0 W The equation of TC1R initial value is like TC1C as following. TC1R initial value = 256 - (TC1 interrupt interval time * input clock) Note: The TC1R is write-only register can't be process by INCMS, DECMS instructions. SONiX TECHNOLOGY CO., LTD Page 84 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC1 TIMER COUNTER OPERATION SEQUENCE The TC1 timer's sequence of operation can be following. Set the TC1C initial value to setup the interval time. Set the TC1ENB to be "1" to enable TC1 timer counter. TC1C is incremented by one with each clock pulse which frequency is corresponding to TC1M selection. TC1C overflow if TC1C from FFH to 00H. When TC1C overflow occur, the TC1IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the TC1C value and resume the TC1 timer operation. Example: Setup the TC1M and TC1C without auto-reload function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET FTC1IEN FTC1ENB A,#20H TC1M,A A,#74H TC1C,A FTC1IEN FTC1IRQ FTC1ENB ; To disable TC1 interrupt service ; To disable TC1 timer ; ; To set TC1 clock = fcpu / 64 ; To set TC1C initial value = 74H ;(To set TC1 interval = 10 ms) ; To enable TC1 interrupt service ; To clear TC1 interrupt request ; To enable TC1 timer Example: Setup the TC1M and TC1C with auto-reload function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC1IEN FTC1ENB A,#20H TC1M,A A,#74H TC1C,A TC1R,A FTC1IEN FTC1IRQ FTC1ENB ALOAD1 ; To disable TC1 interrupt service ; To disable TC1 timer ; ; To set TC1 clock = fcpu / 64 ; To set TC1C initial value = 74H ; (To set TC1 interval = 10 ms) ; To set TC1R auto-reload register ; To enable TC1 interrupt service ; To clear TC1 interrupt request ; To enable TC1 timer ; To enable TC1 auto-reload function. SONiX TECHNOLOGY CO., LTD Page 85 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: TC1 interrupt service routine without auto-reload function. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reload TC1C ; TC1 interrupt service routine ; End of TC1 interrupt service routine and exit interrupt vector FTC1IRQ EXIT_INT FTC1IRQ A,#74H TC1C,A . . EXIT_INT . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector Example: TC1 interrupt service routine with auto-reload. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . JMP . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; TC1 interrupt service routine ; End of TC1 interrupt service routine and exit interrupt vector FTC1IRQ EXIT_INT FTC1IRQ . . EXIT_INT . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 86 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC1 CLOCK FREQUENCY OUTPUT (BUZZER) TC1 timer counter provides a frequency output function. By setting the TC1 clock frequency, the clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1 output signal divides by 2. The TC1 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency. Figure 8-7. The TC1OUT Pulse Frequency Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The TC1OUT frequency is 1KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 2KHz. The TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 131. MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET A,#01100000B TC1M,A A,#131 TC1C,A TC1R,A FTC1OUT FALOAD1 FTC1ENB ; Set the TC1 rate to Fcpu/4 ; Set the auto-reload reference value ; Enable TC1 output to P5.3 and disable P5.3 I/O function ; Enable TC1 auto-reload function ; Enable TC1 timer Note: The TC1OUT frequency table is as TC0OUT frequency table. Please consult TC0OUT frequency table. (Table 7-2~7-5) SONiX TECHNOLOGY CO., LTD Page 87 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PWM FUNCTION DESCRIPTION OVERVIEW PWM function is generated by TC0/TC1 timer counter and output the PWM signal to PWM0OUT pin (P5.4)/ PWM1OUT pin (P5.3). The 8-bit counter counts modulus 256, from 0-255, inclusive. The value of the 8-bit counter is compared to the contents of the reference register (TC0R/TC1R). When the reference register value (TC0R/TC1R) is equal to the counter value (TC0C/TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio (duty) of the PWM0/PWM1 output is TC0R/256 and TC1R/256. All PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value (TC0C/TC1C) changes from FFH back to 00H, the PWM output is forced to high level. The pulse width ratio (duty cycle) is defined by the contents of the reference register (TC0R/TC1R) and is programmed in increments of 1:256. The 8-bit PWM data register TC0R/TC1R is write only register. PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to change the PWM's duty cycle is to modify the TC0R/TC1R. Reference Register Value (TC0R/TC1R) 0000 0000 0000 0001 0000 0010 . . 1000 0000 1000 0001 . . 1111 1110 1111 1111 Duty 0/256 1/256 2/256 . . 128/256 129/256 . . 254/256 255/256 Table 8-5. The PWM Duty Cycle Table 0 TC0/TC1 Clock 1 ..... 128 ..... 254 255 0 1 ..... 128 ..... 254 255 TC0R/TC1R = 00H High Low TC0R/TC1R = 01H High Low TC0R/TC1R = 80H High Low TC0R/TC1R = FFH Low Figure 8-8 The Output of PWM with different TC0R/TC1R. SONiX TECHNOLOGY CO., LTD Page 88 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PWM PROGRAM DESCRIPTION Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The external high-speed oscillator clock is 4MHz. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 30. MOV B0MOV B0MOV MOV MOV B0MOV B0BCLR B0BSET B0BSET A,#01100000B TC0M,A TC0M,A A,#0x00 A,#30 TC0R,A FTC0OUT FPWM0OUT FTC0ENB ; Set the TC0 rate to Fcpu/4 ; Set the TC0 rate to Fcpu/4 ;First Time Initial TC0 ; Set the PWM duty to 30/256 ; Disable TC0OUT function. ; Enable PWM0 output to P5.4 and disable P5.4 I/O function ; Enable TC0 timer Note1: The TC0R and TC1R are write-only registers. Don't process them using INCMS, DECMS instructions. Note2: Set TC0C at initial is to make first duty-cycle correct. After TC0 is enabled, don't modify TC0R value to avoid duty cycle error of PWM output. Example: Modify TC0R/TC1R registers' value. MOV B0MOV INCMS B0MOV B0MOV A, #30H TC0R, A BUF0 A, BUF0 TC0R, A ; Input a number using B0MOV instruction. ; Get the new TC0R value from the BUF0 buffer defined by ; programming. Note3: That is better to set the TC0C and TC0R value together when PWM0 duty modified. It protects the PWM0 signal no glitch as PWM0 duty changing. That is better to set the TC1C and TC1R value together when PWM1 duty modified. It protects the PWM1 signal no glitch as PWM1 duty changing. Note4: The TC0OUT function must be set "0" when PWM0 output enable. The TC1OUT function must be set "0" when PWM1 output enable. Note5: The PWM can work with interrupt request. SONiX TECHNOLOGY CO., LTD Page 89 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 9 INTERRUPT OVERVIEW The SN8P1700 provides 7 interrupt sources, including four internal interrupts (T0, TC0, TC1 & SIO) and three external interrupts (INT0 ~ INT2). These external interrupts can wakeup the chip from power down mode to high-speed normal mode. The external clock input pins of INT0/INT1/INT2 are shared with P0.0/P0.1/P0.2 pins. Once interrupt service is executed, the GIE bit in STKP register will clear to "0" for stopping other interrupt request. When interrupt service exits, the GIE bit will set to "1" to accept the next interrupts' request. All of the interrupt request signals are stored in INTRQ register. The user can program the chip to check INTRQ's content for setting executive priority. 1 The interrupt trigger edge : INT0 ~ INT2 = falling edge INTEN Interrupt enable register T0 time out T0IRQ TC0 time out TC0IRQ Interrupt vector address (0008H) TC1 time out INTRQ 7-bit Latchs TC1IRQ Interrupt enable gating Global interrupt request signal SIO time out SIOIRQ INT0 trigger P00IRQ INT1 trigger P01IRQ INT2 trigger P02IRQ Figure 9-1. The 7 Interrupts of SN8P1700 Note: 1.For SN8P1702 only obtain one internal interrupt P00 and one external interrupt TC0. Note: 2.The GIE bit must enable and all interrupt operations work. SONiX TECHNOLOGY CO., LTD Page 90 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including four internal interrupts, three external interrupts and SIO interrupt enable control bits. One of the register to be set "1" is to enable the interrupt request function. Once of the interrupt occur, the program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed. INTEN initial value = x000 0000 0C9H Bit 7 Bit 6 0 TC1IEN INTEN R/W Bit 5 TC0IEN R/W Bit 4 T0IEN R/W Bit 3 SIOIEN R/W Bit 2 P02IEN R/W Bit 1 P01IEN R/W Bit 0 P00IEN R/W P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable. P01IEN : External P0.1 interrupt control bit. 0 = disable, 1 = enable. P02IEN : External P0.2 interrupt control bit. 0 = disable, 1 = enable. SIOIEN : SIO interrupt control bit. 0 = disable, 1 = enable. T0IEN : T0 timer interrupt control bit. 0 = disable, 1 = enable. TC0IEN : Timer interrupt control bit. 0 = disable, 1 = enable. TC1IEN : Timer interrupt control bit. 0 = disable, 1 = enable. INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of these interrupt request occurs, the bit of the INTRQ register would be set "1". The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. INTRQ initial value = x000 0000 0C8H INTRQ Bit 7 0 - Bit 6 TC1IRQ R/W Bit 5 TC0IRQ R/W Bit 4 T0IRQ R/W Bit 3 SIOIRQ R/W Bit 2 P02IRQ R/W Bit 1 P01IRQ R/W Bit 0 P00IRQ R/W P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request. P01IRQ : External P0.1 interrupt request bit. 0 = non-request, 1 = request. P02IRQ : External P0.2 interrupt request bit. 0 = non-request, 1 = request. SIOIRQ : SIO interrupt request bit. 0 = non-request, 1 = request. T0IRQ : T0 timer interrupt request control bit. 0 = non request, 1 = request. TC0IRQ : TC0 timer interrupt request controls bit. 0 = non request, 1 = request. TC1IRQ : TC1 timer interrupt request controls bit. 0 = non request, 1 = request. When interrupt occurs, the related request bit of INTRQ register will be set to "1" no matter the related enable bit of INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won't execute interrupt vector even when the related bit of INTRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. SONiX TECHNOLOGY CO., LTD Page 91 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC INTERRUPT OPERATION DESCRIPTION SN8P1700 provides 7 interrupts. The operation of the 7 interrupts is as following. GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level. STKP initial value = 0xxx 1111 0DFH STKP Bit 7 GIE R/W Bit 6 - Bit 5 - Bit 4 - Bit 3 STKPB3 R/W Bit 2 STKPB2 R/W Bit 1 STKPB1 R/W Bit 0 STKPB0 R/W GIE: Global interrupt control bit. 0 = disable, 1 = enable. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable and all interrupt operations work. SONiX TECHNOLOGY CO., LTD Page 92 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC INT0 (P0.0) INTERRUPT OPERATION The INT0 is triggered by falling edge. When the INT0 trigger occurs, the P00IRQ will be set to "1" however the P00IEN is enable or disable. If the P00IEN = 1, the trigger event will make the P00IRQ to be "1" and the system enter interrupt vector. If the P00IEN = 0, the trigger event will make the P00IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: INT0 interrupt request setup. B0BSET B0BCLR B0BSET FP00IEN FP00IRQ FGIE ; Enable INT0 interrupt service ; Clear INT0 interrupt request flag ; Enable GIE Example: INT0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check P00IRQ ; P00IRQ = 0, exit interrupt vector ; Reset P00IRQ ; INT0 interrupt service routine FP00IRQ EXIT_INT FP00IRQ . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector Note: The PUSH and POP instruction only save L,H,R,Z,Y,X,PFLAG and RBANK registers but A register. User must save register A by B0XCH instruction when PUSH command is used. INT1 (P0.1) INTERRUPT OPERATION The INT1 is triggered by falling edge. When the INT1 trigger occurs, the P01IRQ will be set to "1" however the P01IEN is enable or disable. If the P01IEN = 1, the trigger event will make the P01IRQ to be "1" and the system enter interrupt vector. If the P01IEN = 0, the trigger event will make the P01IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: INT1 interrupt request setup. B0BSET B0BCLR B0BSET FP01IEN FP01IRQ FGIE ; Enable INT1 interrupt service ; Clear INT1 interrupt request flag ; Enable GIE SONiX TECHNOLOGY CO., LTD Page 93 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: INT1 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn't change C, Z flag ; Push ; Check P01IRQ ; P01IRQ = 0, exit interrupt vector ; Reset P01IRQ ; INT1 interrupt service routine FP01IRQ EXIT_INT FP01IRQ . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector INT2 (P0.2) INTERRUPT OPERATION The INT2 is triggered by falling edge. When the INT2 trigger occurs, the P02IRQ will be set to "1" however the P02IEN is enable or disable. If the P02IEN = 1, the trigger event will make the P02IRQ to be "1" and the system enter interrupt vector. If the P02IEN = 0, the trigger event will make the P02IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: INT2 interrupt request setup. B0BSET B0BCLR B0BSET FP02IEN FP02IRQ FGIE ; Enable INT2 interrupt service ; Clear INT2 interrupt request flag ; Enable GIE Example: INT2 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn' t change C, Z flag ; Push ; Check P02IRQ ; P02IRQ = 0, exit interrupt vector ; Reset P02IRQ ; INT2 interrupt service routine FP02IRQ EXIT_INT FP02IRQ . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 94 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC T0 INTERRUPT OPERATION When the T0C counter occurs overflow, the T0IRQ will be set to "1" however the T0IEN is enable or disable. If the T0IEN = 1, the trigger event will make the T0IRQ to be "1" and the system enter interrupt vector. If the T0IEN = 0, the trigger event will make the T0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: T0 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FT0IEN FT0ENB A, #20H T0M, A A, #74H T0C, A FT0IEN FT0IRQ FT0ENB FGIE ; Disable T0 interrupt service ; Disable T0 timer ; ; Set T0 clock = Fcpu / 64 ; Set T0C initial value = 74H ; Set T0 interval = 10 ms ; Enable T0 interrupt service ; Clear T0 interrupt request flag ; Enable T0 timer ; Enable GIE Example: T0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn' t change C, Z flag ; Push ; Check T0IRQ ; T0IRQ = 0, exit interrupt vector ; Reset T0IRQ ; Reset T0C. ; T0 interrupt service routine FT0IRQ EXIT_INT FT0IRQ A, #74H T0C, A . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 95 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC0 INTERRUPT OPERATION When the TC0C counter occurs overflow, the TC0IRQ will be set to "1" however the TC0IEN is enable or disable. If the TC0IEN = 1, the trigger event will make the TC0IRQ to be "1" and the system enter interrupt vector. If the TC0IEN = 0, the trigger event will make the TC0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: TC0 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC0IEN FTC0ENB A, #20H TC0M, A A, #74H TC0C, A FTC0IEN FTC0IRQ FTC0ENB FGIE ; Disable TC0 interrupt service ; Disable TC0 timer ; ; Set TC0 clock = Fcpu / 64 ; Set TC0C initial value = 74H ; Set TC0 interval = 10 ms ; Enable TC0 interrupt service ; Clear TC0 interrupt request flag ; Enable TC0 timer ; Enable GIE Example: TC0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn' t change C, Z flag ; Push ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; Reset TC0C. ; TC0 interrupt service routine FTC0IRQ EXIT_INT FTC0IRQ A, #74H TC0C, A . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 96 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC TC1 INTERRUPT OPERATION When the TC1C counter occurs overflow, the TC1IRQ will be set to "1" however the TC1IEN is enable or disable. If the TC1IEN = 1, the trigger event will make the TC1IRQ to be "1" and the system enter interrupt vector. If the TC1IEN = 0, the trigger event will make the TC1IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: TC1 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC1IEN FT C1ENB A, #20H TC1M, A A, #74H TC1C, A FTC1IEN FTC1IRQ FTC1ENB FGIE ; Disable TC1 interrupt service ; Disable TC1 timer ; ; Set TC1 clock = Fcpu / 64 ; Set TC1C initial value = 74H ; Set TC1 interval = 10 ms ; Enable TC1 interrupt service ; Clear TC1 interrupt request flag ; Enable TC1 timer ; Enable GIE Example: TC1 interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn' t change C, Z flag ; Push ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reset TC1C. ; TC1 interrupt service routine FTC1IRQ EXIT_INT FTC1IRQ A, #74H TC1C, A . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 97 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SIO INTERRUPT OPERATION When the SIO finished transmitting, the SIOIRQ will be set to "1" however the SIOIEN is enable or disable. If the SIOIEN = 1, the trigger event will make the SIOIRQ to be "1" and the system enter interrupt vector. If the SIOIEN = 0, the trigger event will make the SIOIRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: SIO interrupt request setup. B0BSET B0BCLR B0BSET FSIOIEN FSIOIRQ FGIE ; Enable SIO interrupt service ; Clear SIO interrupt request flag ; Enable GIE Example: SIO interrupt service routine. ORG JMP INT_SERVICE: B0XCH PUSH B0BTS1 JMP B0BCLR . . EXIT_INT: POP B0XCH RETI 8 INT_SERVICE ; Interrupt vector A, ACCBUF ; B0XCH doesn' t change C, Z flag ; Push ; Check SIOIRQ ; SIOIRQ = 0, exit interrupt vector ; Reset SIOIRQ ; SIO interrupt service routine FSIOIRQ EXIT_INT FSIOIRQ . . A, ACCBUF ; Pop ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 98 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC MULTI-INTERRUPT OPERATION In most conditions, the software designer uses more than one interrupt request. Processing multi-interrupt request needs to set the priority of these interrupt requests. The IRQ flags of the 7 interrupt are controlled by the interrupt event occurring. But the IRQ flag set doesn't mean the system to execute the interrupt vector. The IRQ flags can be triggered by the events without interrupt enable. Just only any the event occurs and the IRQ will be logic "1". The IRQ and its trigger event relationship is as the below table. Interrupt Name P00IRQ P01IRQ P02IRQ T0IRQ TC0IRQ TC1IRQ SIOIRQ Trigger Event Description P0.0 trigger. Falling edge. P0.1 trigger. Falling edge. P0.2 trigger. Falling edge. T0C overflow. TC0C overflow. TC1C overflow. End of SIO transmitter operating. There are two things need to do for multi-interrupt. One is to make a good priority for these interrupt requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following. SONiX TECHNOLOGY CO., LTD Page 99 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: How does users check the interrupt request in multi-interrupt situation? ORG B0XCH PUSH INTP00CHK: B0BTS1 JMP B0BTS0 JMP INTP01CHK: B0BTS1 JMP B0BTS0 JMP INTP02CHK: B0BTS1 JMP B0BTS0 JMP INTT0CHK: B0BTS1 JMP B0BTS0 JMP INTTC0CHK: B0BTS1 JMP B0BTS0 JMP INTTC1HK: B0BTS1 JMP B0BTS0 JMP INTSIOCHK: B0BTS1 JMP B0BTS0 JMP INT_EXIT: POP B0XCH RETI 8 A, ACCBUF ; Interrupt vector ; B0XCH doesn' t change C, Z flag ; Push ; Check INT0 interrupt request ; Check P00IEN ; Jump check to next interrupt ; Check P00IRQ ; Jump to INT0 interrupt service routine ; Check INT1 interrupt request ; Check P01IEN ; Jump check to next interrupt ; Check P01IRQ ; Jump to INT1 interrupt service routine ; Check INT2 interrupt request ; Check P02IEN ; Jump check to next interrupt ; Check P02IRQ ; Jump to INT2 interrupt service routine ; Check T0 interrupt request ; Check T0IEN ; Jump check to next interrupt ; Check T0IRQ ; Jump to T0 interrupt service routine ; Check TC0 interrupt request ; Check TC0IEN ; Jump check to next interrupt ; Check TC0IRQ ; Jump to TC0 interrupt service routine ; Check TC1 interrupt request ; Check TC1IEN ; Jump check to next interrupt ; Check TC1IRQ ; Jump to TC1 interrupt service routine ; Check SIO interrupt request ; Check SIOIEN ; Jump to exit of IRQ ; Check SIOIRQ ; Jump to SIO interrupt service routine ; Pop ; Restore ACC value. ; Exit interrupt vector FP00IEN INTP01CHK FP00IRQ INTP00 FP01IEN INTP02CHK FP01IRQ INTP01 FP02IEN INTT0CHK FP02IRQ INTP02 FT0IEN INTTC0CHK FT0IRQ INTT0 FTC0IEN INTTC1CHK FTC0IRQ INTTC0 FTC1IEN INTSIOCHK FTC1IRQ INTTC1 FSIOIEN INT_EXIT FSIOIRQ INTSIO A, ACCBUF SONiX TECHNOLOGY CO., LTD Page 100 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 10 SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) OVERVIEW The SN8P1700provides an 8-bit SIO interface circuit with clock rate selection. The SIOM register can control SIO operating function, such as: transmit/receive, clock rate, transfer edge and starting this circuit. This SIO circuit will TX or RX 8-bit data automatically by setting SENB and START bits in SIOM register. The SIOB is an 8-bit buffer, which is designed to store transfer data. SIOC and SIOR are designed to generate SIO's clock source with auto-reload function. The 3-bit I/O counter can monitor the operation of SIO and announce an interrupt request after transmitting/receiving 8 bits data. After transferring 8-bit data, this circuit will be disabled automatically and re-transfer data by programming SIOM register. Senb SI/P5.1 pin Sckmd SCK/P5.0 pin CPUM1,0 SCK sources CPUM1,0 SIOC 8-bit binary counter Senb Srate Auto_reload SIOR register Senb Data bus SIOM register Senb, TxRx SO/P5.2 pin SIOB 8-bit buffer CPUM1,0 3-bit I/O counter Sckmd Sedge reset Senb SIO Time out Figure 10-1. SIO Interface Circuit Diagram SONiX TECHNOLOGY CO., LTD Page 101 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Figure 9-2 shows a typical transfer between two microcontrollers. Process 1 sends SCK for initial the data transfer. Both processors must work in the same clock edge direction, then both controllers would send and receive data at the same time. SDI SDO SIOM Register SIOM Register SIOB 8 Bit Buffer MSB LSB SDO SDI SIOB 8 Bit Buffer MSB LSB SIO Clock SCK PROCESS 1 SCK PROCESS 2 Figure 10-2. SIO Data Transfer Diagram SIOM MODE REGISTER SIOM initial value = 0000 x000 0B4H SIOM Bit 7 SENB R/W Bit 6 START R/W Bit 5 SRATE1 R/W Bit 4 SRATE0 R/W Bit 3 0 - Bit 2 SCKMD R/W Bit 1 SEDGE R/W Bit 0 TXRX R/W SENB: SIO function control bit. 0 = disable (P5.0~P5.2 is general purpose port), 1 = enable (P5.0~P5.2 is SIO pins). START: SIO progress control bit. 0 = End of transfer, 1 = progressing. SRATE1, 0: SIO's transfer rate select bit. 00 = fcpu, 01 = fcpu/32, 10 = fcpu/16, 11 = fcpu/8. (Note: These 2-bits are workless when SCKMD=1) SCKMD: SIO's clock mode select bit. 0 = internal, 1 = external mode. SEDGE: SIO's transfer clock edge select bit. 0 = falling edge, 1 = raising edge. TXRX: SIO's transfer direction select bit. 0 = receiver only , 1 = transmitter/receiver full duplex. Note 1: If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock, the SIO is in MASTER mode. Note 2: Don't set SENB and START bits in the same time. That makes the SIO function error. SONiX TECHNOLOGY CO., LTD Page 102 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Because SIO function is shared with Port5 for P5.0 as SCK, P5.1 as SI and P5.2 as SO The following table shown the Port5[2:0] I/O mode behavior and setting when SIO function enable and disable SENB=1 (SIO Function Enable) (SCKMD=1) P5.0/SCK SIO source = External clock (SCKMD=0) SIO source = Internal clock P5.1/SI P5.0 will change to Input mode automatically, no matter what P5M setting P5.0 will change to Output mode automatically, no matter what P5M setting P5.1 must be set as Input mode in P5M ,or the SIO function will be abnormal (TXRX=1) P5.2 will change to Output mode automatically, no matter what P5M setting P5.2 will change to Input mode automatically, no matter what P5M setting P5.2/SO SIO = Transmitter/Receiver (TXRX=0) SIO = Receiver only SENB=0 (SIO Function Disable) P5.0/P5.1/P5.2 Port5[2:0] I/O mode are fully controlled by P5M when SIO function Disable SIOB DATA BUFFER SIOB initial value = 0000 0000 0B6H SIOB Bit 7 X R/W Bit 6 X R/W Bit 5 X R/W Bit 4 X R/W Bit 3 X R/W Bit 2 X R/W Bit 1 X R/W Bit 0 X R/W SIOB is the SIO data buffer register. It stores serial I/O transmit and receive data. SIOR REGISTER DESCRIPTION SIOR initial value = 0000 0000 0B5H SIOR Bit 7 X W Bit 6 X W Bit 5 X W Bit 4 X W Bit 3 X W Bit 2 X W Bit 1 X W Bit 0 X W The SIOR is designed for the SIO counter to reload the counted value when end of counting. It is like a post-scaler of SIO clock source and let SIO has more flexible to setting SCK range. Users can set the SIOR value to setup SIO transfer time. To setup SIOR value equation to desire transfer time is as following. SCK frequency = SIO rate / (256 - SIOR) SIOR = 256 - ( 1 / ( SCK frequency ) * SIO rate / 2 ) Example: Setup the SIO clock to be 5KHz. Fosc = 3.58MHz. SIO's rate = Fcpu = Fosc/4. SIOR = 256 - (1/(5KHz) * 3.58MHz/4) = 256 - 89 = 167 SONiX TECHNOLOGY CO., LTD Page 103 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SIO MASTER OPERATING DESCRIPTION Under master-transmitter situation, the SCK has two directions as following. SCK SCK Figure 10-3. The Two SCK Directions of SIO Master Operation RISING EDGE TRANSMITTER/RECEIVER MODE Example: Master Tx/Rx rising edge MOV B0MOV MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,TXDATA SIOB,A A,#0FFH SIOR,A A,#10000011B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Load transmitted data into SIOB register. ; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Rising edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. TX/RX data SCK SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO DO0 LSB DO1 DO2 DO3 DO4 DO5 DO6 DO7 MSB Figure 10-4. The Rising Edge Timing Diagram of Master Transfer and Receiving Operation SONiX TECHNOLOGY CO., LTD Page 104 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC FALLING EDGE TRANSMITTER/RECEIVER MODE Example: Master Tx/Rx falling edge MOV B0MOV MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,TXDATA SIOB,A A,#0FFH SIOR,A A,#10000001B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Load transmitted data into SIOB register. ; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Falling edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. TX/RX data SCK SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO DO0 LSB DO1 DO2 DO3 DO4 DO5 DO6 DO7 MSB Figure 10-5. The Falling Edge Timing Diagram of Master Transfer and Receiving Operation SONiX TECHNOLOGY CO., LTD Page 105 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC RISING EDGE RECEIVER MODE Example: Master Rx rising edge MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,#0FFH SIOR,A A,#10000010B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Rising edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. RX data SCK SI DI0 LSB DI1 DI2 DI3 DI4 DI5 DI6 DI7 MSB SO Normal I/O Application Figure 10-6. The Rising Edge Timing Diagram of Master Receiving Operation SONiX TECHNOLOGY CO., LTD Page 106 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC FALLING EDGE RECEIVER MODE Example: Master Rx falling edge MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,#0FFH SIOR,A A,#10000000B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Set SIO clock with auto-reload function. ; Setup SIOM and enable SIO function. Falling edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. RX data SCK SI DI0 LSB DI1 DI2 DI3 DI4 DI5 DI6 DI7 MSB SO Normal I/O Application Figure 10-7. The Falling Edge Timing Diagram of Master Receiving Operation SONiX TECHNOLOGY CO., LTD Page 107 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SIO SLAVE OPERATING DESCRIPTION Under slave-receiver situation, the SCK has four phases as following. SCK1 SCK2 SCK3 SCK4 Figure 10-8. The Four Phases SCK clock of SIO Slave Operation. SONiX TECHNOLOGY CO., LTD Page 108 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC RISING EDGE TRANSMITTER/RECEIVER MODE Example: Slave Tx/Rx rising edge MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,TXDATA SIOB,A A,# 10000111B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Load transfer data into SIOB register. ; Setup SIOM and enable SIO function. Rising edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. TX/RX data SCK1 SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO DO0 LSB TX/RX data DO1 DO2 DO3 DO4 DO5 DO6 DO7 MSB SCK2 SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO DO0 LSB DO1 DO2 DO3 DO4 DO5 DO6 DO7 MSB Figure 10-9. The Rising Edge Timing Diagram of Slave Transfer and Receiving Operation SONiX TECHNOLOGY CO., LTD Page 109 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC FALLING EDGE TRANSMITTER/RECEIVER MODE Example: Slave Tx/Rx falling edge MOV B0MOV MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,TXDATA SIOB,A A,# 10000101B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Load transfer data into SIOB register. ; Setup SIOM and enable SIO function. Falling edge. ; Start transfer and receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. TX/RX data SCK3 SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO DO0 LSB TX/RX data DO1 DO2 DO3 DO4 DO5 DO6 DO7 MSB SCK4 SI DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 SO DO0 LSB DO1 DO2 DO3 DO4 DO5 DO6 DO7 MSB Figure 10-10. The Falling Edge Timing Diagram of Slave Transfer and Receiving Operation SONiX TECHNOLOGY CO., LTD Page 110 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC RISING EDGE RECEIVER MODE Example: Slave Rx rising edge MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,# 10000110B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Setup SIOM and enable SIO function. Rising edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. RX data SCK3 SI DI0 LSB DI1 DI2 DI3 DI4 DI5 DI6 DI7 MSB SO RX data Normal I/O Application SCK4 SI DI0 LSB DI1 DI2 DI3 DI4 DI5 DI6 DI7 MSB SO Normal I/O Application Figure 10-11. The Rising Edge Timing Diagram of Slave Receiving Operation SONiX TECHNOLOGY CO., LTD Page 111 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC FALLING EDGE RECEIVER MODE Example: Slave Rx falling edge MOV B0MOV B0BSET CHK_END: B0BTS0 JMP B0MOV MOV A,# 10000100B SIOM,A FSTART FSTART CHK_END A,SIOB RXDATA,A ; Setup SIOM and enable SIO function. Falling edge. ; Start receiving SIO data. ; Wait the end of SIO operation. ; Save SIOB data into RXDATA buffer. RX data SCK1 SI DI0 LSB DI1 DI2 DI3 DI4 DI5 DI6 DI7 MSB SO RX data Normal I/O Application SCK2 SI DI0 LSB DI1 DI2 DI3 DI4 DI5 DI6 DI7 MSB SO Normal I/O Application Figure 10-12. The Falling Edge Timing Diagram of Slave Receiving Operation SONiX TECHNOLOGY CO., LTD Page 112 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SIO INTERRUPT OPERATION DESCRIPTION The SIO provides an interrupt function. Users can process SIO data after the SIO interrupt request occurring. There is a example for the application as following. Example: SIO interrupt demo routine. Main: MOV B0MOV B0BSET . . JMP A,# 10000100B SIOM,A FSTART . . MAIN ; Setup SIOM and enable SIO function. Falling edge. ; Start transfer SIO data. ORG B0XCH PUSH B0BTS1 JMP B0MOV MOV B0BCLR INT_EXIT: POP B0XCH 8 A, ACCBUF ; Interrupt vector FSIOIRQ INT_EXIT A,SIOB RXDATA,A FSIOIRQ ; Save SIOB data into RXDATA buffer. ; Clear SIO interrupt request flag. A, ACCBUF SONiX TECHNOLOGY CO., LTD Page 113 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 11 I/O PORT OVERVIEW The SN8P1700 provides up to 5 ports for users' application, consisting of one input only port (P0), four I/O ports (P1, P2, P4, P5). The direction of I/O port is selected by PnM register and a macro @SET_PUR is defined for user setting pull-up register. After the system resets, all ports work as input function without pull-up resistors. Port1, 2, 4, 5 structure Port0 structure PUR PUR PnM PnM Pin Pin Int. bus PnM Latch Int. bus Figure 11-1. The I/O Port Block Diagram Note : All of the latch output circuits are push-pull structures. SONiX TECHNOLOGY CO., LTD Page 114 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC I/O PORT FUNCTION TABLE Port/Pin I/O Function Description General-purpose input function External interrupt (INT0~INT2) Wakeup for power down mode General-purpose input/output function Wakeup for power down mode General-purpose input/output function General-purpose input/output function ADC analog signal input General-purpose input/output function SIO clock pin. General-purpose input/output function SIO data input pin. General-purpose input/output function SIO data output pin. General-purpose input/output function Table 11-1. I/O Function Table Remark P0.0~P0.2 P1.0~P1.5 P2.0~P2.7 P4.0~P4.7 P5.0 P5.1 P5.2 P5.3~P5.7 I I/O I/O I/O I/O I/O I I/O O I/O P5M.1 must be set "0" P5M.1 must be set "1" SONiX TECHNOLOGY CO., LTD Page 115 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC PULL-UP RESISTERS SN8P1700 series chips built-in pull-up resisters in port 0, port 1, port4 and port 5. For MASK type compatible issues, SONIX 8-bit MCU assembler provide a @SET_PUR macro to control pull-up resisters. @SET_PUR macro only allows enable or disable pull-up resisters as a whole port. SN8P1702 / SN8P1704: @SET_PUR VAL I/O Port Port 7 VAL Bit 7 Disable Pull-up Fixed "0" Enable Pull-up Port 6 Bit 6 Fixed "0" Port 5 Bit 5 0 1 Port 4 Bit 4 0 1 Port 3 Bit 3 Fixed "0" Port 2 Bit 2 Fixed "0" Port 1 Bit 1 0 1 Port 0 Bit 0 0 1 SN8P1706 / SN8P1707 / SN8P1708: @SET_PUR VAL I/O Port Port 7 Port 6 VAL Bit 7 Bit 6 Disable Pull-up Fixed "0" Fixed "0" Enable Pull-up Port 5 Bit 5 0 1 Port 4 Bit 4 0 1 Port 3 Bit 3 Fixed "0" Port 2 Bit 2 0 1 Port 1 Bit 1 0 1 Port 0 Bit 0 0 1 Example 1: Enable port 0 and port 1 pull-up resisters and disable others CHIP SN8P1708 ORG 0x10 Main: . . @SET_PUR 0x03 ; Enable port 0 and port 1 pull-up resisters Example 2: Enable all pull-up resisters CHIP SN8P1708 ORG 0x10 Main: . . @SET_PUR 0x37 ; Enable port 0, port 1, port 4 and port 5 pull-up resisters Note: a. Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup in sleep mode. b. SN8P1704 and SN8P1702 must call @SET_PUR at least one time to avoid sleep mode fail. SONiX TECHNOLOGY CO., LTD Page 116 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC I/O PORT MODE The port direction is programmed by PnM register. Port 0 is always input mode. Port 1,2,4 and 5 can select input or output direction. P1M initial value = xx00 0000 0C1H P1M Bit 7 0 - Bit 6 0 - Bit 5 P15M R/W Bit 4 P14M R/W Bit 3 P13M R/W Bit 2 P12M R/W Bit 1 P11M R/W Bit 0 P10M R/W P10M~P15M: P1.0~P1.5 I/O direction control bit. 0 = input mode, 1 = output mode. P2M initial value = 0000 0000 0C2H P2M Bit 7 P27M R/W Bit 6 P26M R/W Bit 5 P25M R/W Bit 4 P24M R/W Bit 3 P23M R/W Bit 2 P22M R/W Bit 1 P21M R/W Bit 0 P20M R/W P20M~P27M: P2.0~P2.7 I/O direction control bit. 0 = input mode, 1 = output mode. P4M initial value = 0000 0000 0C4H P4M Bit 7 P47M R/W Bit 6 P46M R/W Bit 5 P45M R/W Bit 4 P44M R/W Bit 3 P43M R/W Bit 2 P42M R/W Bit 1 P41M R/W Bit 0 P40M R/W P40M~P47M: P4.0~P4.7 I/O direction control bit. 0 = input mode, 1 = output mode. P5M initial value = 0000 0000 0C5H P5M Bit 7 P57M R/W Bit 6 P56M R/W Bit 5 P55M R/W Bit 4 P54M R/W Bit 3 P53M R/W Bit 2 P52M R/W Bit 1 P51M R/W Bit 0 P50M R/W P50M~P57M: P5.0~P5.7 I/O direction control bit. 0 = input mode, 1 = output mode. The each bit of PnM is set to "0", the I/O pin is input mode. The each bit of PnM is set to "1", the I/O pin is output mode. Input mode is with pull-up resistor controlled by setting @SET_UP macro. The output mode disables the pull-up resistors no matter pull-up resistors is set or not. The PnM registers are read/write bi-direction registers. Users can program them by bit control instructions (B0BSET, B0BCLR). SONiX TECHNOLOGY CO., LTD Page 117 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: I/O mode selecting. CLR CLR CLR CLR P1M P2M P4M P5M ; Set all ports to be input mode. MOV B0MOV B0MOV B0MOV B0MOV A, #0FFH P1M, A P2M, A P4M, A P5M, A ; Set all ports to be output mode. B0BCLR B0BSET P1M.5 P1M.5 ; Set P1.5 to be input mode. ; Set P1.5 to be output mode. SONiX TECHNOLOGY CO., LTD Page 118 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC I/O PORT DATA REGISTER P0 initial value = xxxx x000 0D0H P0 Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 P02 R Bit 1 P01 R Bit 0 P00 R P1 initial value = xx00 0000 0D1H P1 Bit 7 - Bit 6 - Bit 5 P15 R/W Bit 4 P14 R/W Bit 3 P13 R/W Bit 2 P12 R/W Bit 1 P11 R/W Bit 0 P10 R/W P2 initial value = 0000 0000 0D2H P2 Bit 7 P27 R/W Bit 6 P26 R/W Bit 5 P25 R/W Bit 4 P24 R/W Bit 3 P23 R/W Bit 2 P22 R/W Bit 1 P21 R/W Bit 0 P20 R/W P4 initial value = 0000 0000 0D4H P4 Bit 7 P47 R/W Bit 6 P46 R/W Bit 5 P45 R/W Bit 4 P44 R/W Bit 3 P43 R/W Bit 2 P42 R/W Bit 1 P41 R/W Bit 0 P40 R/W P5 initial value = 0000 0000 0D5H P5 Bit 7 P57 R/W Bit 6 P56 R/W Bit 5 P55 R/W Bit 4 P54 R/W Bit 3 P53 R/W Bit 2 P52 R/W Bit 1 P51 R/W Bit 0 P50 R/W Example: Read data from input port. B0MOV B0MOV B0MOV B0MOV B0MOV A, P0 A, P1 A, P2 A, P4 A, P5 ; Read data from Port 0 ; Read data from Port 1 ; Read data from Port 2 ; Read data from Port 4 ; Read data from Port 5 Example: Write data to output port. MOV B0MOV B0MOV B0MOV B0MOV A, #55H P1, A P2, A P4, A P5, A ; Write data 55H to Port 1, Port2, Port 4, Port 5 SONiX TECHNOLOGY CO., LTD Page 119 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC Example: Write one bit data to output port. B0BSET B0BSET B0BCLR B0BCLR P1.3 P4.0 P2.3 P5.5 ; Set P1.3 and P4.0 to be "1". ; Set P2.3 and P5.5 to be "0". Example: Port bit test. B0BTS1 . B0BTS0 P0.0 P1.5 ; Bit test 1 for P0.0 ; Bit test 0 for P1.5 SONiX TECHNOLOGY CO., LTD Page 120 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 12 8-CHANNEL ANALOG TO DIGITAL CONVERTER OVERVIEW This analog to digital converter of SN8P1700 has 8-input sources with up to 4096-step resolution to transfer analog signal into 12-bits digital data. The sequence of ADC operation is to select input source (AIN0 ~ AIN7) at first, then set GCHS and ADS bit to "1" to start conversion. When the conversion is complete, the ADC circuit will set EOC bit to "1" and final value output in ADB register. This ADC circuit can select between 8-bit and 12-bit resolution operation by programming ADLEN bit in ADR register. AIN0/P4.0 AIN1/P4.1 AIN2/P4.2 DATA BUS AIN3/P4.3 AIN4/P4.4 AIN5/P4.5 AIN6/P4.6 AIN7/P4.7 Figure 12-1. AD Converter Function Diagram A/D CONVERTER (ADC) 8/12 Note: For 8-bit resolution the conversion time is 12 steps. For 12-bit resolution the conversion time is 16 steps. Note: The analog input level must be between the AVREFH and AVSS. Note: The AVREFH level must be between the AVDD and AVSS. SONiX TECHNOLOGY CO., LTD Page 121 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ADM REGISTER ADM initial value = 0000 x000 0B1H ADM Bit 7 ADENB R/W Bit 6 ADS R/W Bit 5 EOC R/W Bit 4 GCHS R/W Bit 3 - Bit 2 CHS2 R/W Bit 1 CHS1 R/W Bit 0 CHS0 R/W CHS2, 1, 0: ADC input channels select bit. 000 = AIN0, 001 = AIN1, 010 = AIN2, 011 = AIN3, .. , 111 = AIN7. GCHS: Global channel select bit. 0 = To disable AIN channel, 1 = To enable AIN channel. EOC: ADC status bit. 0 = Progressing, 1 = End of converting and reset ADENB bit. ADS: ADC start bit. 0 = stop, 1 = starting. ADENB: ADC control bit. 0 = disable, 1 = enable. ADR REGISTERS ADR initial value = x00x 0000 0B3H ADR Bit 7 - Bit 6 ADCKS R/W Bit 5 ADLEN R/W Bit 4 0 - Bit 3 ADB3 R Bit 2 ADB2 R Bit 1 ADB1 R Bit 0 ADB0 R ADBn: ADC data buffer. ADB11~ADB4 bits for 8-bit ADC. ADB11~ADB0 bits for 12-bit ADC. ADLEN: ADC's resolution select bits. 0 = 8-bit, 1 = 12-bit. ADCKS: ADC's clock source select bit. ADCKS 0 1 ADC clock source Fcpu/4 Fhosc Note Both validate in Normal mode and Slow mode Only validate in Normal mode ADB REGISTERS ADB initial value = xxxx xxxx 0B2H ADB Bit 7 ADB11 R Bit 6 ADB10 R Bit 5 ADB9 R Bit 4 ADB8 R Bit 3 ADB7 R Bit 2 ADB6 R Bit 1 ADB5 R Bit 0 ADB4 R ADB is ADC data buffer to store AD converter result. The ADB is only 8-bit register including bit 4~bit11 ADC data. To combine ADB register and the low-nibble of ADR will get full 12-bit ADC data buffer. The ADC buffer is a read-only register. In 8-bit ADC mode, the ADC data is stored in ADB register. In 12-bit ADC mode, the ADC data is stored in ADB and ADR registers. SONiX TECHNOLOGY CO., LTD Page 122 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC The AIN's input voltage v.s. ADB's output data ADB1 ADB10 ADB9 1 0/4096*AVREFH 0 0 0 1/4096*AVREFH 0 0 0 . . . . . . . . . . . . 4094/4096*AVREFH 1 1 1 4095/4096*AVREFH 1 1 1 AIN n ADB8 0 0 . . . 1 1 ADB7 0 0 . . . 1 1 ADB6 0 0 . . . 1 1 ADB5 0 0 . . . 1 1 ADB4 0 0 . . . 1 1 ADB3 0 0 . . . 1 1 ADB2 0 0 . . . 1 1 ADB1 0 0 . . . 1 1 ADB0 0 1 . . . 0 1 For different applications, users maybe need more than 8-bit resolution but less than 12-bit ADC converter. To process the ADB and ADR data can make the job well. First, the AD resolution must be set 12-bit mode and then to execute ADC converter routine. Then delete the LSB of ADC data and get the new resolution result. The table is as following. ADC ADB11 Resolution 8-bit O 9-bit O 10-bit O 11-bit O 12-bit O O = Selected, x = Delete ADB ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADR ADB2 ADB1 ADB0 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O x O O O O x x O O O x x x O O x x x x O SONiX TECHNOLOGY CO., LTD Page 123 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ADC CONVERTING TIME 12-bit ADC conversion time = 1/(ADC clock /4)*16 sec 8-bit ADC conversion time = 1/(ADC clock /4)*12 sec High clock (fosc) is @3.58MHz ADLEN 0 (8-bit) 1 (12-bit) ADCKS0 0 1 0 1 ADC Clock Fcpu/4 Fhosc Fcpu/4 Fhosc ADC conversion time 1/((3.58MHz/4)/4/4)*12 = 214.5 us 1/(3.58MHz/4)*12 = 13.4 us 1/((3.58MHz/4)/4/4)*16 = 286 us 1/(3.58MHz/4)*16 = 17.9 us Example : To set AIN0 ~ AIN1 for ADC input and executing 12-bit ADC ADC0: MOV B0MOV MOV B0MOV B0BSET WADC0: B0BTS1 JMP B0MOV ADC1: MOV B0MOV B0BSET . QEXADC: B0BCLR FGCHS ; To release AINx input channel A,#91H ADM,A FADS . ; ; To enable ADC and set AIN1 input ; To start conversion . FEOC WADC0 A,ADB ; To skip, if end of converting =1 ; else, jump to WADC0 ; To get AIN0 input data A, #60H ADR, A A,#90H ADM,A FADS ; To set 12-bit ADC and ADC clock = Fosc. ; To enable ADC and set AIN0 input ; To start conversion SONiX TECHNOLOGY CO., LTD Page 124 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ADC CIRCUIT VDD AVREF Analog Signal Input 0.1uF AIN0/P40 MCU AVREFH is connected to VDD. VDD Reference Voltage Input Analog Signal Input 47uF 0.1uF AVREF AIN0/P40 MCU AVREFH is connected to external AD reference voltage. Figure 12-2. The AINx and AVREFH Circuit of AD Converter Note: The capacitor between AIN and GND is a bypass capacitor. It is helpful to stable the analog signal. Users can omit it. SONiX TECHNOLOGY CO., LTD Page 125 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 13 7-BIT DIGITAL TO ANALOG CONVERTER OVERVIEW The D/A converter uses 7-bit structure to synthesize 128 steps' analog signal with current source output. After DAENB bit is set to "1", DAC circuit will turn to be enabled and the DAM register, from bit0 to bit6, will send digital signal to ladder resistors in order to generate analog signal on DAO pin. DAM REGISTER LADDER RESISTORS DAO OUTPUT Figure 13-1. The DA converter Block Diagram In order to get a proper linear output, a Loading Resistor RL is usually added between DAO and Ground. The example shows the result of Vdd = 5V, RL =150ohm and Vdd = 3V, RL =150ohm. Vdd=5V Vdd=3V Figure 13-2 DAO Circuit with RL Figure 13-3. DAC Output Voltage in Vdd=5V and 3V The D/A converter is not designed for a precise DC voltage output and is suitable for a simple audio application e.g. Tone or Melody generation. DAM REGISTER DAM initial value = 0000 0000 0B0H DAM Bit 7 DAENB R/W Bit 6 DAB6 R/W Bit 5 DAB5 R/W Bit 4 DAB4 R/W Bit 3 DAB3 R/W Bit 2 DAB2 R/W Bit 1 DAB1 R/W Bit 0 DAB0 R/W DAENB: Digital to Analog converter control bit. 0 = disable, 1 = enable. DABn: Digital input data. SONiX TECHNOLOGY CO., LTD Page 126 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC D/A CONVERTER OPERATION When the DAENB = 0, the DAO pin is output floating status. After setting DAENB to "1", the DAO output value is controlled by DAB bits. Example: Output 1/2 VDD from DAO pin. MOV B0MOV B0BSET A, #00111111B DAM, A FDAENB ; Set DAB to a half of the full scale. ; Enable D/A function. The DAB's data v.s. DAO's output voltage as following: DAB6 0 0 0 0 . . . 1 1 DAB5 0 0 0 0 . . . 1 1 7 DAB4 0 0 0 0 . . . 1 1 DAB3 0 0 0 0 . . . 1 1 DAB2 0 0 0 0 . . . 1 1 DAB1 0 0 1 1 . . . 1 1 DAB0 0 1 0 1 . . . 0 1 DAO VSS Idac 2 * Idac 3 * Idac . . . 126 * Idac 127 * Idac Table 13-1. DAB and DAO Relative Table Note: Idac = IFSO / (2 -1) (IFSO: Full-scale Output Current) SONiX TECHNOLOGY CO., LTD Page 127 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 14 CODING ISSUE TEMPLATE CODE ;******************************************************************************* ; FILENAME : TEMPLATE.ASM ; AUTHOR : SONiX ; PURPOSE : Template Code for SN8X17XX ; REVISION : 09/01/2002 V1.0 First issue ;******************************************************************************* ;* (c) Copyright 2002, SONiX TECHNOLOGY CO., LTD. ;******************************************************************************* CHIP SN8P1708 ; Select the CHIP ;------------------------------------------------------------------------------; Include Files ;------------------------------------------------------------------------------.nolist ; do not list the macro file INCLUDESTD INCLUDESTD INCLUDESTD .list MACRO1.H MACRO2.H MACRO3.H ; Enable the listing function ;------------------------------------------------------------------------------; Constants Definition ;------------------------------------------------------------------------------; ONE EQU 1 ;------------------------------------------------------------------------------; Variables Definition ;------------------------------------------------------------------------------.DATA org DS DS DS DS org DS 0h 1 1 1 1 100h 20 ;Bank 0 data section start from RAM address 0x000 ;Temporary buffer for main loop ;Temporary buffer for ISR ;Accumulater buffer ;PFLAG buffer ;Bank 1 data section start from RAM address 0x100 ;Temporary buffer in bank 1 Wk00B0 Iwk00B0 AccBuf PflagBuf BufB1 ;------------------------------------------------------------------------------; Bit Flag Definition ;------------------------------------------------------------------------------Wk00B0_0 EQU Wk00B0.0 ;Bit 0 of Wk00B0 Iwk00B0_1 EQU Iwk00B0.1 ;Bit 1 of Iwk00 ;------------------------------------------------------------------------------- SONiX TECHNOLOGY CO., LTD Page 128 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ; Code section ;------------------------------------------------------------------------------.CODE ORG jmp ORG jmp 0 Reset 8 Isr ;Code section start ;Reset vector ;Address 4 to 7 are reserved ;Interrupt vector ORG 10h ;------------------------------------------------------------------------------; Program reset section ;------------------------------------------------------------------------------Reset: mov A,#07Fh ;Initial stack pointer and b0mov STKP,A ;disable global interrupt b0mov PFLAG,#00h ;pflag = x,x,x,x,x,c,dc,z b0mov RBANK,#00h ;Set initial RAM bank in bank 0 mov A,#40h ;Clear watchdog timer and initial system mode b0mov OSCM,A call call b0bset ClrRAM SysInit FGIE ;Clear RAM ;System initial ;Enable global interrupt ;------------------------------------------------------------------------------; Main routine ;------------------------------------------------------------------------------Main: b0bset FWDRST ;Clear watchdog timer call jmp MnApp Main ;------------------------------------------------------------------------------; Main application ;------------------------------------------------------------------------------MnApp: ; Put your main program here ret ;----------------------------------; Jump table routine ;----------------------------------ORG 0x0100 ;The jump table should start from the head ;of boundary. b0mov A,Wk00 and A,#3 ADD PCL,A jmp JmpSub0 jmp JmpSub1 jmp JmpSub2 ;----------------------------------- SONiX TECHNOLOGY CO., LTD Page 129 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC JmpSub0: ; Subroutine 1 jmp JmpExit JmpSub1: ; Subroutine 2 jmp JmpExit JmpSub2: ; Subroutine 3 jmp JmpExit JmpExit: ret ;Return Main ;------------------------------------------------------------------------------; Isr (Interrupt Service Routine) ; Arguments : ; Returns : ; Reg Change: ;------------------------------------------------------------------------------Isr: ;----------------------------------; Save ACC and system registers ;----------------------------------b0xch A,AccBuf ;B0xch instruction do not change C,Z flag push ;Remark this line in SN8P1702 registers ;Save 80h ~ 87h system ;Following two lines for SN8X1702 only ;b0mov A,PFLAG ;b0mov PflagBuf,A ;----------------------------------; Check which interrupt happen ;----------------------------------IntP00Chk: b0bts1 jmp b0bts0 jmp FP00IEN IntTc0Chk FP00IRQ P00isr ;Modify this line for another interrupt ;If necessary, insert another interrupt checking here IntTc0Chk: b0bts1 jmp b0bts0 jmp FTC0IEN IsrExit FTC0IRQ TC0isr ;Suppose TC0 is the last interrupt which you ;want to check SONiX TECHNOLOGY CO., LTD Page 130 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ;----------------------------------; Exit interrupt service routine ;----------------------------------IsrExit: ; Following two lines for SN8X1702 only ;b0mov A,PFLAG ;b0mov PflagBuf,A pop b0xch reti A,AccBuf ;Remark this line in SN8P1702 ;Restore 80h ~ 87h system registers ;B0xch instruction do not change C,Z flag ;Exit the interrupt routine ;------------------------------------------------------------------------------; INT0 interrupt service routine ;------------------------------------------------------------------------------P00isr: b0bclr FP00IRQ ;Process P0.0 external interrupt here jmp IsrExit ;------------------------------------------------------------------------------; TC0 interrupt service routine ;------------------------------------------------------------------------------TC0isr: b0bclr FTC0IRQ ;Process TC0 timer interrupt here jmp IsrExit ;------------------------------------------------------------------------------; SysInit ; Initialize I/O, Timer, Interrupt, etc. ;------------------------------------------------------------------------------SysInit: ret SONiX TECHNOLOGY CO., LTD Page 131 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC ;------------------------------------------------------------------------------; ClrRAM ; Use index @YZ to clear RAM (00h~7Fh) ;------------------------------------------------------------------------------ClrRAM: ; RAM Bank 0 clr b0mov ClrRAM10: clr decms jmp clr ; RAM Bank 1 mov b0mov b0mov ClrRAM20: clr decms jmp clr ret Y Z,#0x7f ;Select bank 0 ;Set @YZ address from 7fh @YZ Z ClrRAM10 @YZ ;Clear @YZ content ;z = z - 1 , skip next if z=0 ;Clear address 0x00 A,#1 Y,A Z,#0x7f ;Select bank 1 ;Set @YZ address from 17fh @YZ Z ClrRAM20 @YZ ;Clear @YZ content ;z = z - 1 , skip next if z=0 ;Clear address 0x100 ;------------------------------------------------------------------------------ENDP SONiX TECHNOLOGY CO., LTD Page 132 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC CHIP DECLARATION IN ASSEMBLER Assembler CHIP SN8P1702 CHIP SN8P1704 CHIP SN8P1706 CHIP SN8P1707 CHIP SN8P1708 OTP Device Part Number SN8P1702 SN8P1704 SN8P1706 SN8P1707 SN8P1708 MASK Device Part Number SN8A1702A SN8A1704A SN8A1706A SN8A1707A SN8A1708A PROGRAM CHECK LIST Item Pull-up Resister Description Use @SET_PUR macro to enable or disable on-chip pull-up resisters. Refer I/O port chapter for detailed information. All bits those are marked as "0" (undefined bits) in system registers should be set "0" to avoid unpredicted system errors. Set ADC input pin I/O direction as input mode and disable pull-up resister of ADC input pin Set SCK (P5.0) and SO (P5.2) pin as output mode. Set SI (P5.1) pin as input mode. Set SO (P5.2) pin as output mode. Set SCK (P5.0) and SI (P5.1) pin as input mode. Set PWM0 (P5.4) pin as output mode. Set PWM1 (P5.3) pin as output mode. Do not enable interrupt before initializing RAM. Non-used I/O ports should be pull-up or pull-down in input mode, or be set as low in output mode to save current consumption. Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup. Be careful of function call and interrupt service routine operation. Don't let stack buffer overflow or underflow. 1. Write 0x7F into STKP register to initial stack pointer and disable global interrupt Undefined Bits ADC SIO Master Mode SIO Slave Mode PWM0 PWM1 Interrupt Non-Used I/O Sleep Mode Stack Buffer System Initial 2. Clear all RAM. 3. Initialize all system register even unused registers. 1. Enable OSG and High_Clk / 2 code option together 2. Enable the watchdog option to protect system crash. 3. Non-used I/O ports should be set as output low mode Noisy Immunity 4. Constantly refresh important system registers and variables in RAM to avoid system crash by a high electrical fast transient noise. 5. Enable the LVD option to improve the power on reset or brown-out reset performance SONiX TECHNOLOGY CO., LTD Page 133 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 15 INSTRUCTION SET TABLE Field M O V E Mnemonic Description C - DC - Z Cycle 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 2 2 2 2 1 1 1 - MOV MOV B0MOV B0MOV MOV B0MOV XCH B0XCH MOVC ADC ADC ADD ADD B0ADD ADD SBC SBC SUB SUB SUB DAA MUL AND AND AND OR OR OR XOR XOR XOR SWAP SWAPM RRC RRCM RLC RLCM CLR BCLR BSET B0BCLR B0BSET CMPRS CMPRS INCS INCMS DECS DECMS BTS0 BTS1 B0BTS0 B0BTS1 JMP CALL RET RETI PUSH POP NOP @SET_PUR A,M M,A A,M M,A A,I M,I A,M A,M A,M M,A A,M M,A M,A A,I A,M M,A A,M M,A A,I A,M A,M M,A A,I A,M M,A A,I A,M M,A A,I M M M M M M M M.b M.b M.b M.b A,I A,M M M M M M.b M.b M.b M.b d d AM MA A M (bnak 0) M (bank 0) A AI M I, (M = only for Working registers R, Y, Z , RBANK & PFLAG) A M A M (bank 0) R, A ROM [Y,Z] A A + M + C, if occur carry, then C=1, else C=0 M A + M + C, if occur carry, then C=1, else C=0 A A + M, if occur carry, then C=1, else C=0 M A + M, if occur carry, then C=1, else C=0 M (bank 0) M (bank 0) + A, if occur carry, then C=1, else C=0 A A + I, if occur carry, then C=1, else C=0 A A - M - /C, if occur borrow, then C=0, else C=1 M A - M - /C, if occur borrow, then C=0, else C=1 A A - M, if occur borrow, then C=0, else C=1 M A - M, if occur borrow, then C=0, else C=1 A A - I, if occur borrow, then C=0, else C=1 To adjust ACC's data format from HEX to DEC. R, A A * M, The LB of product stored in Acc and HB stored in R register. ZF affected by Acc. A A and M M A and M A A and I A A or M M A or M A A or I A A xor M M A xor M A A xor I A (b3~b0, b7~b4) M(b7~b4, b3~b0) M(b3~b0, b7~b4) M(b7~b4, b3~b0) A RRC M M RRC M A RLC M M RLC M M0 M.b 0 M.b 1 M(bank 0).b 0 M(bank 0).b 1 ZF,C A - I, If A = I, then skip next instruction ZF,C A - M, If A = M, then skip next instruction A M + 1, If A = 0, then skip next instruction M M + 1, If M = 0, then skip next instruction A M - 1, If A = 0, then skip next instruction M M - 1, If M = 0, then skip next instruction If M.b = 0, then skip next instruction If M.b = 1, then skip next instruction If M(bank 0).b = 0, then skip next instruction If M(bank 0).b = 1, then skip next instruction PC15/14 RomPages1/0, PC13~PC0 d Stack PC15~PC0, PC15/14 RomPages1/0, PC13~PC0 d PC Stack PC Stack, and to enable global interrupt To push working registers (080H~087H) into buffers To pop working registers (080H~087H) from buffers No operation Enable or disable pull-up resisters. Bit N of VAL: "0" disable port N pull-up, "1" enable port N pull-up A R I T H M E T I C L O G I C P R O C E S S B R A N C H M I S C VAL Table 15-1. Instruction Set Table of SN8P1700 Note 1: Any instruction that read/write from 0SCM, will add an extra cycle.) Note 2: SN8P1702/SN8A1702 don't provide "MUL, PUSH, POP" instruction. SONiX TECHNOLOGY CO., LTD Page 134 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 16 ELECTRICAL CHARACTERISTIC ABSOLUTE MAXIMUM RATING (All of the voltages referenced to Vss) Supply voltage (Vdd)............................................................................................................... - 0.3V ~ 6.0V Input in voltage (Vin)..................................................................................................Vss - 0.2V ~ Vdd + 0.2V Operating ambient temperature (Topr)......................................................................................-20C ~ + 70C Storage ambient temperature (Tstor).......................................................................................-30C ~ + 125C Power consumption (Pc).................................................................................................................500 mW STANDARD ELECTRICAL CHARACTERISTIC SN8P1700 Series (OTP) (All of voltages referenced to Vss, Vdd = 5.0V, fosc = 3.579545 MHz, ambient temperature is 25C unless otherwise note.) PARAMETER SYM. DESCRIPTION MIN. TYP. MAX. UNIT Normal mode, Vpp = Vdd 2.2 5.0 5.5 Operating voltage Vdd V Programming mode, Vpp = 12.5V 4.5 5.0 5.5 RAM Data Retention voltage Vdr 1.5 V Internal POR Vpor Vdd rise rate to ensure internal power-on reset 0.05 V/ms ViL1 All input pins except those specified below Vss 0.3Vdd V ViL2 Input with Schmitt trigger buffer - Port0 Vss 0.2Vdd V Input Low Voltage ViL3 Reset pin ; Xin ( in RC mode ) Vss 0.2Vdd V ViL4 Xin ( in X'tal mode ) Vss 0.3Vdd V ViH1 All input pins except those specified below 0.7Vdd Vdd V ViH2 Input with Schmitt trigger buffer -Port0 0.8Vdd Vdd V Input High Voltage ViH3 Reset pin ; Xin ( in RC mode ) 0.9Vdd Vdd V ViH4 Xin ( in X'tal mode ) 0.7Vdd Vdd V Reset pin leakage current Ilekg Vin = Vdd 2 uA I/O port pull-up resistor Rup Vin = Vss , Vdd = 5V 100 K I/O port input leakage current Ilekg Pull-up resistor disable, Vin = Vdd 2 uA Port1 output source current IoH Vop = Vdd - 0.5V 12 mA sink current IoL Vop = Vss + 0.5V 15 Port2 output source current IoH Vop = Vdd - 0.5V 12 mA sink current IoL Vop = Vss + 0.5V 15 Port4 output source current IoH Vop = Vdd - 0.5V 12 mA sink current IoL Vop = Vss + 0.5V 15 Port5 output source current IoH Vop = Vdd - 0.5V 12 mA sink current IoL Vop = Vss + 0.5V 15 INTn trigger pulse width Tint0 INT0 ~ INT2 interrupt request pulse width 2/fcpu cycle AVREFH input voltage Varef Vdd = 5.0V 1.2V Vdd V AIN0 ~ AIN7 input voltage Vani Vss+0.2 Avref V Fosc Crystal type or ceramic resonator 32768 4M 16M Oscillator Frequency Hz VDD = 3V, RC type for external mode 6M VDD = 5V, RC type for external mode 10M Vdd= 5V 4Mhz 7 15 mA Idd1 Run Mode Vdd= 3V 4Mhz 1.5 3 mA Vdd= 3V 32768Hz 50 100 uA Supply Current Vdd= 5V 32KHz Int RC 80 150 uA Slow mode (Disable ADC and LVD) Idd2 (Stop High Clock) Vdd= 3V 16KHz Int RC 15 30 uA Vdd= 5V 10 18 uA Idd3 Sleep mode Vdd= 3V 3 6 uA LVD Detect Voltage Vdet Low voltage detect level 2.4 V Voltage detector current Ivdet LVD enable operating current 100 180 uA Vdd=5.0V 0.6 1 mA ADC current consumption IADC Vdd=3.0V 0.4 0.8 mA DAC Full-scale Output Current IFSO Vdd=5V, RL =150ohm 12 mA SONiX TECHNOLOGY CO., LTD Page 135 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC 17 PACKAGE INFORMATION P-DIP18 PIN Symbols A A1 A2 D E E1 L B MIN. 0.015 0.125 0.880 0.245 0.115 0.335 0 NOR. 0.130 0.900 0.300BSC. 0.250 0.130 0.355 7 MAX. 0.210 0.135 0.920 0.255 0.150 0.375 15 UNIT : INCH SONiX TECHNOLOGY CO., LTD Page 136 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SOP18 PIN Symbols A A1 D E H L MIN. 0.093 0.004 0.447 0.291 0.394 0.016 0 MAX. 0.104 0.012 0.463 0.299 0.419 0.050 8 UNIT : INCH SONiX TECHNOLOGY CO., LTD Page 137 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SSOP20 PIN Symbols A A1 A2 b b1 C C1 D E E1 e h L L1 ZD Y MIN, 1.35 0.10 0.20 0.20 0.18 0.18 8.56 5.80 3.80 0.25 0.40 1.00 0 DIMENSION (MM) NOM. 1.60 0.15 0.254 0.254 0.203 0.203 8.66 6.00 3.90 0.635 BSC 0.42 0.635 1.05 1.50 REF - MAX. 1.75 0.25 1.50 0.30 0.28 0.25 0.23 8.74 6.20 4.00 0.50 1.27 1.10 0.10 8 MIN. 53 4 8 8 7 7 337 228 150 10 16 39 0 DIMENSION (MIL) NOM. 63 6 10 11 8 8 341 236 154 25 BSC 17 25 41 58 REF - MAX. 69 10 59 12 11 10 9 344 244 157 20 50 43 4 8 SONiX TECHNOLOGY CO., LTD Page 138 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC S-DIP28 PIN Symbols A A1 A2 D E E1 L B MIN. 0.015 0.114 1.390 0.283 0.115 0.330 0 NOR. 0.130 1.390 0.310BSC. 0.288 0.130 0.350 7 MAX. 0.210 0.135 1.400 0.293 0.150 0.370 15 UNIT : INCH SONiX TECHNOLOGY CO., LTD Page 139 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SOP28 PIN Symbols A A1 D E H L MIN. 0.093 0.004 0.697 0.291 0.394 0.016 0 MAX. 0.104 0.012 0.713 0.299 0.419 0.050 8 UNIT : INCH SONiX TECHNOLOGY CO., LTD Page 140 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC QFP 44 PIN SYMBOLS A A1 A2 b C D D1 E E1 L [e] MIN 0.010 0.075 0.004 0.512 0.390 0.512 0.390 0.029 0 NOR (inch) 0.012 0.079 0.012 0.006 0.520 0.394 0.520 0.394 0.035 0.031 - MAX 0.106 0.014 0.087 0.008 0.528 0.398 0.528 0.398 0.037 7 MIN 0.250 1.900 0.100 13.000 9.900 13.000 9.900 0.730 0 NOR (mm) 0.300 2.000 0.300 0.150 13.200 10.000 13.200 10.000 0.880 0.800 - MAX 2.700 0.350 2.200 0.200 13.400 10.100 13.400 10.100 0.930 7 SONiX TECHNOLOGY CO., LTD Page 141 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SSOP 48 PIN SYMBOLS A A1 A2 b C D E [e] He L L1 Y MIN 0.095 0.008 0.089 0.008 0.620 0.291 0.396 0.020 0 NOR (inch) 0.102 0.012 0.094 0.010 0.008 0.625 0.295 0.025 0.406 0.030 0.056 - MAX 0.110 0.016 0.099 0.030 0.630 0.299 0.416 0.040 0.003 8 MIN 2.413 0.203 2.261 0.203 15.748 7.391 10.058 0.508 0 NOR (mm) 2.591 0.305 2.388 0.254 0.203 15.875 7.493 0.635 10.312 0.762 1.422 - MAX 2.794 0.406 2.515 0.762 16.002 7.595 10.566 1.016 0.076 8 SONiX TECHNOLOGY CO., LTD Page 142 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC P-DIP 48 PIN SYMBOLS A A1 A2 D E E1 L MIN 0.015 0.150 2.400 0.540 0.115 0.630 0 NOR (inch) 0.155 2.450 0.600 0.545 0.130 0.650 7 MAX 0.220 0.160 2.550 0.550 0.150 0.067 15 MIN 0.381 3.810 60.960 13.716 2.921 16.002 0 NOR (mm) 3.937 62.230 15.240 13.843 3.302 16.510 7 MAX 5.588 4.064 64.770 13.970 3.810 1.702 15 B SONiX TECHNOLOGY CO., LTD Page 143 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC P-DIP 40 PIN SYMBOLS A A1 A2 D E E1 L MIN 0.015 0.150 2.055 0.540 0.115 0.630 0 NOR (inch) 0.115 2.060 0.600 0.545 0.130 0.650 7 MAX 0.220 0.160 2.070 0.550 0.150 0.067 15 MIN 0.381 3.810 52.197 13.716 2.921 16.002 0 NOR (mm) 2.921 52.324 15.240 13.843 3.302 16.510 7 MAX 5.588 4.064 52.578 13.970 3.810 1.702 15 B SONiX TECHNOLOGY CO., LTD Page 144 Revision 1.94 SN8P1700 8-bit micro-controller build-in 12-bit ADC SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. Main Office: Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C. Tel: 886-3-551 0520 Fax: 886-3-551 0523 Taipei Office: Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C. Tel: 886-2-2759 1980 Fax: 886-2-2759 8180 Hong Kong Office: Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon. Tel: 852-2723 8086 Fax: 852-2723 9179 Technical Support by Email: Sn8fae@sonix.com.tw SONiX TECHNOLOGY CO., LTD Page 145 Revision 1.94 |
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